
ML401/ML402/ML403 Evaluation Platform
21
UG080 (v2.5) May 24, 2006
Detailed Description
R
Single-Ended Expansion I/O Connectors
Header J6 contains 32 single-ended signal connections to the FPGA I/Os. This permits the
signals on this connector to carry high-speed single-ended data. All single-ended signals
on connector J6 are matched length traces. The V
CCIO
of these signals can be set to 2.5V or
3.3V by setting jumper J16.
(spans onto next page) summarizes the single-ended
connections on this expansion I/O connector.
Table 10:
Expansion I/O Single-Ended Connections (J6)
Header Pin
Label
FPGA Pin
J6, Pin 2
HDR1_28
AA24
J6, Pin 4
HDR1_42
V20
J6, Pin 6
HDR1_36
AC25
J6, Pin 8
HDR1_2
AC24
J6, Pin 10
HDR1_52
W25
J6, Pin 12
HDR1_32
AB24
J6, Pin 14
HDR1_26
Y24
J6, Pin 16
HDR1_12
AB23
J6, Pin 18
HDR1_50
W26
J6, Pin 20
HDR1_38
Y26
J6, Pin 22
HDR1_40
Y25
J6, Pin 24
HDR1_22
AA26
J6, Pin 26
HDR1_10
AA23
J6, Pin 28
HDR1_60
AC21
J6, Pin 30
HDR1_24
AB26
J6, Pin 32
HDR1_4
AC23
J6, Pin 34
HDR1_30
AB25
J6, Pin 36
HDR1_6
AD23
J6, Pin 38
HDR1_34
AC26
J6, Pin 40
HDR1_18
AD26
J6, Pin 42
HDR1_16
AC22
J6, Pin 44
HDR1_54
V22
J6, Pin 46
HDR1_56
V21
J6, Pin 48
HDR1_46
W22
J6, Pin 50
HDR1_20
AD25
J6, Pin 52
HDR1_14
AB22
J6, Pin 54
HDR1_48
W21
J6, Pin 56
HDR1_44
W20
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