Xilinx M401, User Manual, Page: 11 / 32

ML401/ML402/ML403 Evaluation Platform www.xilinx.com 11
UG080 (v2.5) May 24, 2006
Introduction
R
Block Diagram
Figure 1 shows a block diagram of the ML40 x evaluation platform (board).
Figure 1: Virtex-4 ML40 x Evaluation Platform Block Diagram
Virtex-4
FPGA
UG0 8 0_01_050506
GPIO
(Button/LED/DIP Switch)
100 MHz XTAL + User
SMA
(Differiential In/Out Clocks)
Dual PS/2
FLASH
FLASH
Sync
RAM
CPLD
Platform Flash
S y s tem ACE
Controller
SEL MAP SL
V SERIAL
JT
A
G
JT
A
G
JT
A
G
JT
A
G
JT
A
G
MSTR SERL
I/O Expansion Header
USB
Controller
10/100/1000
Enet PHY
AC97
Audio CODEC
16 X 32
Character LCD
CF PC
DDR SDRAM
DDR SDRAM
RS-232 XCVR
Video
IIC EEPROM
RJ-45
Line Out/
Headphone
Mic In /
Line In
VGA
Serial
Host
Peripheral
Peripheral
32
32
32
32 16
TPS54310
3A SWIFT
TPS54610
6A SWIFT
TPS51100
3A DDR LDO
TPS73118
150mA LDO
TPS54310
3A SWIFT
5V Brick
3A
1.25V
to VTT
1.2V
2.5V
5V to USB and PS/2
2.5V to DDR SDRAM
to FPGA Core
3.3V
to FPGA I/O
1.8V
to PROM
User IIC Bus
Note: The DIP switch is
not available on the
ML403 board
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