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Ethernet AVB Endpoint User Guide
UG492 September 21, 2010
Chapter 15:
Detailed Example Design (Standard Format)
<component name>/implement
The implement directory contains the core implementation script files.
rx_frame_checker.v[hd]
An HDL file which is capable of receiving
Ethernet frames at maximum line rate.
This will check the data contained in each
Ethernet frame received against a
predictable pattern. This file partners the
tx_frame_stimulus file.
plb_client_logic.v[hd]
An HDL file that sits in the place of an
embedded microprocessor (an
embedded microprocessor is required in
a real system), which provides stimulus
to the PLB, performing write and reads
that initiate PTP frame transmission.
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Table 15-4:
Example Design Directory
(Cont’d)
Name
Description
Table 15-5:
Implement Directory
Name
Description
<project_dir>/<component_name>/implement
implement.sh
LINUX shell script that processes the
example design through the Xilinx tool flow.
See
“Implementation Scripts,” page 151
for
more information.
implement.bat
Windows batch file that processes the
example design through the Xilinx tool flow.
See
“Implementation Scripts,” page 151
for
more information.
xst.prj
XST project file for the example design
(VHDL only); it enumerates all of the VHDL
files that need to be synthesized.
xst.scr
XST script file for the example design.
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Summary of Contents for LogiCORE Endpoint v2.4
Page 1: ...LogiCORETM IP Ethernet AVB Endpoint v2 4 User Guide UG492 September 21 2010...
Page 8: ...8 www xilinx com Ethernet AVB Endpoint User Guide UG492 September 21 2010...
Page 12: ...12 www xilinx com Ethernet AVB Endpoint User Guide UG492 September 21 2010...
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