Xilinx LogiCORE Endpoint v2.4, User Manual

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36 www.xilinx.com Ethernet AVB Endpoint User Guide
UG492 September 21, 2010
Chapter 4: Generating the Core
Component Name
The component name is used as the base name of the output files generated for the core.
Names must begin with a letter and must be composed from the following characters: a
through z, 0 through 9 and “_”.
Core Delivery Format
The Ethernet AVB Endpoint core can be delivered in two different formats, selectable from
this section of the CORE Generator software Customization GUI:
•
Standard CORE Generator software format (provided for the standard ISE software
environment)
This option will deliver the core in the standard CORE Generator software output
format, as used by many other cores including previous versions of this core and all
other Ethernet LogiCORE™ IP solutions.
When generated in this format, the core is designed to interface to the LogiCORE IP
Tri-Mode Ethernet MAC or the LogiCORE IP Embedded Tri-Mode Ethernet MAC
wrappers (available in selected Virtex® families). See
Chapter 12, “System
Integration” .
When generated in this format, “Ethernet AVB GUI Page 2” is available for
customization of the “PLB Interface” .
•
Generate as an EDK pcore (provided for the Embedded Development Kit)
This option will deliver the core in the standard pcore format, suitable for directly
importing into the Xilinx Embedded Development Kit (EDK) environment.
When generated in this format, the core is designed to interface to the XPS LocalLink
Tri-Mode Ethernet MAC (xps_ll_temac). See
Chapter 12, “System Integration” .
When generated in this format, page 2 of the GUI is not available; the “PLB Interface”
will be configured dynamically by the EDK Xilinx Platform Studio (XPS) software.
For directory and file definitions for the two available formats, see Chapter 15, “Detailed
Example Design (Standard Format)” and Chapter 16, “Detailed Example Design (EDK
format).”