Xilinx LogiCORE Endpoint v2.4, User Manual

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Ethernet AVB Endpoint User Guide www.xilinx.com 113
UG492 September 21, 2010
Using the Xilinx LogiCORE IP Tri-Mode Ethernet MACs
Connections Without Ethernet Statistics
Figure 12-1 illustrates the connection of the Ethernet AVB Endpoint core to the Xilinx Tri-
Mode Ethernet MAC (TEMAC) core when not using the Ethernet Statistics core.
Figure 12-1 provides detail for the connections between the two cores which were shown
in Figure 5-1 .
All connections, as shown, are logic-less connections. Because the AVB standard does not
include support for half-duplex or flow control operation, the relevant half-duplex/flow-
control signals of the TEMAC can be left unused: inputs can be tied to logic 0, outputs can
be left unconnected.
X-Ref Target - Figure 12-1
Figure 12-1: Connection to the Tri-Mode Ethernet MAC Core (without Ethernet Statistics)
tx_clk
tx_clk_en
tx_d a t a [7:0]
rx_clk
rx_clk_en
rx_d a t a [7:0]
rx_d a t a _v a lid
rx_fr a me_good
rx_fr a me_ ba d
ho s t_opcode[1:0]
ho s t_ a ddr[9:0]
ho s t_wr_d a t a [ 3 1:0]
ho s t_re q
ho s t_miim_ s el
ho s t_miim_rdy
ho s t_rd_d a t a _m a c[ 3 1:0]
ho s t_rd_d a t a _ s t a t s [ 3 1:0]
ho s t_ s t a t s _l s w_rdy
ho s t_ s t a t s _m s w_rdy
ho s t_clk
p aus e_re q
tx_clk
tx_clk_en
tx_d a t a [7:0]
tx_colli s ion
tx_retr a n s mit
rx_clk
rx_clk_en
rx_d a t a [7:0]
rx_fr a me_good
rx_d a t a _v a lid
rx_fr a me_ ba d
ho s t_opcode[1:0]
ho s t_ a ddr[9:0]
ho s t_wr_d a t a [ 3 1:0]
ho s t_re q
ho s t_miim_ s el
ho s t_miim_rdy
ho s t_rd_d a t a [ 3 1:0]
ho s t_clk
ho s t_clk
NC
NC
NC
NC
GND
NC
NC
GND
GND
tx_d a t a _v a lid
tx_ u nderr u n
tx_ a ck
tx_d a t a _v a lid
tx_ u nderr u n
tx_ a ck
tx_ifg_del a y[7:0]
p aus e_v a l[15:0]
rx_ s t a ti s tic s _v a lid
tx_ s t a ti s tic s _vector[ 3 1:0]
rx_ s t a ti s tic s _vector[27:0]
tx_ s t a ti s tic s _v a lid
TEMAC Block-level Wr a pper
(from TEMAC Ex a mple De s ign)
Ethernet AVB Endpoint
Core Netli s t