Xilinx Alveo X3522 User Manual Download Page 62 | Manualshive

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Alveo Documents

1. Alveo X3522 Data Sheet (

)

2. Alveo X3522 Installation Guide (

3. Alveo Card Debug Guide (

)

4. Alveo Data Center Accelerator Card Platforms User Guide (

Onload Documents

1. Onload User Guide (

)

2. TCPDirect User Guide (

3. ef_vi User Guide (

)

4. Alveo X3 ef_vi Conversion Guide (

Precision Time Protocol Documents

1. Enhanced PTP User Guide (

Additional Xilinx Resources

1. Xilinx licensing website:

https://www.xilinx.com/getproduct

2. Vitis Developer Zone:

https://www.xilinx.com/products/design-tools/vitis/vitis-platform.html

3. Xilinx Community Forums:

https://forums.xilinx.com

4.

Xilinx Third-Party End User License Agreement

5.

End-User License Agreement

Revision History

The following table shows the revision history for this document.

Section

Revision Summary

10/18/2022 Version 1.0

Initial release.

N/A

Appendix A: Additional Resources and Legal Notices

UG1523 (v1.0) October 18, 2022

Alveo X3522 User Guide

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Summary of Contents for Alveo X3522

Page 1: ...ge from our products and related collateral We ve launched an internal initiative to remove language that could exclude people or reinforce historical biases including terms embedded in our software a...

Page 2: ...smit 15 Interrupts 17 Filtering 17 Ports 17 Drivers 18 Features 19 Tuning 19 Chapter 4 Basic Configuration 21 Supported Speed and Mode 21 Status LEDs 21 Basic Adapter Configuration 22 UEFI and PXE 23...

Page 3: ...7 Teaming Bonding 52 Setting Up Teams 52 Chapter 8 Statistics and Logging 53 Linux ethtool Statistics 53 Reading Sensors 56 Driver Logging Levels 60 Appendix A Additional Resources and Legal Notices 6...

Page 4: ...Onload and EnterpriseOnload unless otherwise stated Users of Onload should refer to the Onload User Guide UG1586 which describes procedures for download and installation of the Onload distribution acc...

Page 5: ...0238 NC SI NC SI and DSP0222 PLDM Monitoring and control DSP0248 Preboot UEFI Data integrity ECC protected memories Single bit error correction Double bit error detection Diagnostics Initiate self gen...

Page 6: ...Ethernet link ARP Address Resolution Protocol Maps IP addresses to MAC addresses BASE R FEC A type of Forward Error Correction also known as Firecode CPU Central Processing Unit CTPIO Cut Through Prog...

Page 7: ...performance user level network stack from Xilinx which accelerates TCP and UDP network I O PCIe Peripheral Component Interconnect Express A high speed serial bus used to connect components PF Physical...

Page 8: ...Table 2 Terms and Definitions cont d Term Definition XCUX35 The FPGA used on an X3522 Chapter 1 Introduction UG1523 v1 0 October 18 2022 www xilinx com Alveo X3522 User Guide 8 Send Feedback...

Page 9: ...r and are shared between applications Applications that share a queue should run on cores that share their L3 cache Explicit huge pages are required TX always uses CTPIO with 16 apertures per port ins...

Page 10: ...vlink or ethtool Linux utilities are instead used for update configuration and information See Chapter 6 Programming the X3522 Higher Power Requirement Power draw varies more with traffic load The X35...

Page 11: ...supported Overlapped receives are not supported You must ensure PIO is not enabled i e set the attribute pio 0 Dynamically linked applications that do not have any of the preceding issues can be used...

Page 12: ...w PCIe vendor ID It will then be treated in the same way as other Xilinx Solarflare NICs No changes are needed to configuration See the Enhanced PTP User Guide UG1602 Chapter 2 X3 Migration Quickstart...

Page 13: ...1000s of VIs that can be allocated to applications on demand The X3522 has entirely separate receive and transmit queues that can be allocated more flexibly They can be directed to separate event que...

Page 14: ...rs multiple packets at a fixed stride 2 KB to each super buffer The super buffers are allocated using explicit huge pages All super buffers for an RX queue are held in a single pool The driver owns th...

Page 15: ...nsmitting packets on the X3522 is Cut Through Programmed I O CTPIO This has been heavily updated compared to its predecessors to reduce latency and make it more robust The X2522 has a single CTPIO tra...

Page 16: ...between processes running on the same CPU cluster Each transmit aperture has an associated event queue The common use case is for each transmit aperture to have a separate event queue that is consumed...

Page 17: ...dware only actions a single filter even if subsequent filters would also match the packet There is no hardware replication of packets to deliver to multiple queues The hardware has mechanisms so that...

Page 18: ...er and application libraries such as Onload and TCPDirect The xilinx_efct and auxiliary bus drivers can both be downloaded from the product website see Product Website The auxiliary bus driver is also...

Page 19: ...mps Yes Yes Jumbo frame support Yes No RX queues Multiple separate queues Shared queue TX types DMA PIO CTPIO CTPIO only Number of filters 16384 total 256 per port Types of filter 3 or 5 part IP MAC a...

Page 20: ...d Onload sending is always done with CTPIO and this uses more CPU than sending with DMA The net driver refills the RX ring Depending on traffic rate it might need more CPU time The net driver must che...

Page 21: ...e speed It is recommended to configure the link properties on the connected switch port and leave the adapter in its default state Status LEDs Each DSFP28 cage has two adjacent LEDs showing the status...

Page 22: ...ED for a cage is Blinking green when there is link activity on all exposed network ports for the cage Off when there is no activity on any exposed network port for the cage Note Some other LEDs inside...

Page 23: ...ere are 2048 descriptor entries per ring The user can identify and reconfigure the receive ring buffer size using the ethtool command Note Transmit on the X3522 does not use a ring buffer and so you c...

Page 24: ...nts PXE The host can then use the UEFI functions of the X3522 NIC to run PXE over that NIC Precision Time Protocol Customers requiring configuration instructions for these adapters and Xilinx PTP in a...

Page 25: ...rk acceleration technologies Onload TCPDirect ef_vi Determine the Minimum Number of Huge Pages To determine the minimum number of huge pages that are required 1 Determine the number of receive queues...

Page 26: ...ket buffers ethtool g interface For example ethtool g enp1s0f0np0 Ring parameters for enp1s0f0np0 Pre set maximums RX 6144 RX Mini 0 RX Jumbo 0 TX 512 Current hardware settings RX 2048 RX Mini 0 RX Ju...

Page 27: ...le on the system HugePages_Free is the number of huge pages that are free on the system 2 If too few huge pages are free allocate some extra huge pages For example to configure a total of 1024 huge pa...

Page 28: ...Us that use the same L3 cache This is because if multiple applications install filters to receive the same traffic they will share a receive queue at least for that traffic When choosing which CPU to...

Page 29: ...alues set by the X3522 driver To disable irqbalance permanently run sbin chkconfig level 12345 irqbalance off To see whether irqbalance is currently running run sbin service irqbalance status To disab...

Page 30: ...ive and transmit queues To determine and set interrupt affinity for the receive and transmit queues use the following commands To view the interrupts assigned to a particular interface ls sys class ne...

Page 31: ...0 0 PCI MSI 49283078 edge enp1s0f0np0 rx 6 128 0 0 0 0 0 0 0 0 PCI MSI 49283079 edge enp1s0f0np0 rx 7 130 18 0 1 0 0 0 31 0 PCI MSI 49283080 edge enp1s0f0np0 tx 0 As applications start the interrupts...

Page 32: ...rmine the associations between queues and CPU cores and to change them if necessary Set the CPU and Receive Queue for your Application Now that you have determined the layout of your processor and rec...

Page 33: ...hat was specified for the ethtool rule 5 When your application quits delete the ethtool rule ethtool N interface delete rule number For example to delete rule 0 that was installed in step above ethtoo...

Page 34: ...arriving through interface interface reaching the kernel insert a filter to drop it As root use the following command ethtool N interface flow type udp4 dst ip 224 0 0 0 m 15 255 255 255 action 1 wher...

Page 35: ...ng in end to end mode sudo ethtool N enp2s0f0np0 flow type udp4 dst ip 224 0 1 129 dst port 319 action 0 Added rule with ID 0 sudo ethtool N enp2s0f0np0 flow type udp4 dst ip 224 0 1 129 dst port 320...

Page 36: ...the interval expires A new moderation interval then starts during which no interrupt is raised An event that occurs after the moderation interval has expired gets its own dedicated interrupt that is r...

Page 37: ...moderation is disabled for applications that require best latency and jitter performance such as market data handling Interrupt moderation is enabled for high throughput single or few connection TCP...

Page 38: ...tocol Tuning TCP performance can also be improved by tuning kernel TCP settings Settings include adjusting send and receive buffer sizes connection backlog congestion control etc Initial buffering set...

Page 39: ...temporarily sbin service cpuspeed stop The service can be disabled across reboots sbin chkconfig level 12345 cpuspeed off CPU Power Service On RHEL7 systems cpuspeed is replaced with cpupower It is re...

Page 40: ...ly has fewer than 8 lanes X3522 adapters require a PCIe Gen 4 8 or Gen 3 8 slot for optimal performance The X3522 driver will warn if it detects that the adapter is placed in a sub optimal slot Warnin...

Page 41: ...on you might need to consider other issues influencing performance such as application settings server motherboard chipset CPU speed cache size RAM size additional software installed on the system suc...

Page 42: ...ult Enabled TCP protocol tuning Leave at default but changing does not impact latency Interrupt affinity irqbalance service Interrupt affinity settings are application dependent Stop irqbalance servic...

Page 43: ...rwarding Tuning Settings Tuning Parameter How TCP IP checksum offload Leave at default Enabled TCP protocol tuning Leave at default Interrupt affinity irqbalance service Interrupt affinity Affinitize...

Page 44: ...ages The file is known as a bundle The images in a bundle are tested together and are known to work with each other You can change the behavior of the X3522 The update file contains an image of user c...

Page 45: ...uct Website 2 Download the required package as identified in the following sections Update to Latest Version To update all partitions of the FPGA to the latest version download one of the following bu...

Page 46: ...on the x86 host On the remote server scp path_to_package root x86_host_ip_address tmp or on the x86 host scp username remote_host path_to_package tmp 3 Install the update files from the package For an...

Page 47: ...4 Wait for the firmware to finish the update viewing the progress report from devlink devlink dev flash pci 0000 01 00 0 file xilinx x3 x3 bundle update Checking update Starting update Erasing 100 Wri...

Page 48: ...pdate Ethtool blocks and does not report progress Completion is indicated by ethtool exiting and the command line prompt appearing Note If you press Ctrl C it halts ethtool but the firmware continues...

Page 49: ...linx PCIe devices for the X3522 including one or more Ethernet controllers lspci D d 10ee 0000 01 00 0 Ethernet controller Xilinx Corporation Device 5084 0000 01 00 1 Ethernet controller Xilinx Corpor...

Page 50: ...fw psid field devlink dev info pci 0000 01 00 0 pci 0000 01 00 0 driver xilinx_efct serial_number serial_number versions fixed board id X3522 running stored fw psid configuration 3 Confirm that the re...

Page 51: ...fetchable size 1M Memory at 2fffe01000 64 bit prefetchable size 4K Capabilities Confirm Hybrid Mode Enablement To determine whether hybrid mode is enabled and so the adapter is programmable you can us...

Page 52: ...ming configuration support provided by the Linux bonding driver includes 802 3ad dynamic link aggregation Static link aggregation Fault tolerance To set up an adapter team consult the following docume...

Page 53: ...rt_ are from the physical adapter port Other statistics are from the specified PCIe function The following table lists the complete output from the ethtool S command Note ethtool S output depends on t...

Page 54: ...alid pause op_code port_rx_unicast Number of unicast packets received port_rx_multicast Number of multicast packets received port_rx_broadcast Number of broadcasted packets received port_rx_lt64 Numbe...

Page 55: ...he adapter port speed The packet is truncated and data transmitted as a poisoned packet port_ctpio_success Number of successful CTPIO TX events ptp_invalid_sync_windows Number of times that the PTP wi...

Page 56: ...r to receive packets has failed rx_broadcast_drop Number of received broadcast packets that have been dropped rx_other_host_drop Number of received packets dropped because the MAC address does not mat...

Page 57: ...apter PCI adapter xilinx_u25_gen3x8 ea_blp_1_user pci 0601 Adapter PCI adapter The list includes Devices for the Ethernet controller on the X3522 card Further devices that are associated with other PC...

Page 58: ...gh 100 0 C crit 110 0 C 12V PCI 1 94 A min 0 00 A max 5 50 A 3V3 AUX PCI 0 06 A min 0 00 A max 0 38 A 3V3 PCI 0 49 A min 0 00 A max 2 10 A VCCINT OUT 16 50 A min 0 00 A max 0 00 A Reading Sensor Value...

Page 59: ...INT OUT in0_label VCC0V85 in10_label 3V3 PCI in11_label VCCINT OUT in1_label VCC1V8 in2_label 1V2VCCO in3_label 1V2AVTT in4_label 0V9AVCC in5_label 3V3 in6_label 3V3 CAGES in7_label 5V0 in8_label 12V...

Page 60: ...ng netif msg txt A message will only appear on the terminal console if both the kernel console log level and netif message level requirements are met The current netif message level can be viewed usin...

Page 61: ...s Xilinx Design Tools DocNav At the Linux command prompt enter docnav Xilinx Design Hubs provide links to documentation organized by design tasks and other topics which you can use to learn key concep...

Page 62: ...ide UG1602 Additional Xilinx Resources 1 Xilinx licensing website https www xilinx com getproduct 2 Vitis Developer Zone https www xilinx com products design tools vitis vitis platform html 3 Xilinx C...

Page 63: ...y display the Materials without prior written consent Certain products are subject to the terms and conditions of Xilinx s limited warranty please refer to Xilinx s Terms of Sale which can be viewed a...

Page 64: ...brands included herein are trademarks of Xilinx in the United States and other countries PCI PCIe and PCI Express are trademarks of PCI SIG and used under license All other trademarks are the property...

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