Xilinx Alveo X3522, User Manual

Page: 6 / 64

Figure 1: X3522 Block Diagram
QSPI Secondary
Flash
XCUX35-3VSVA1365E
Satellite
Controller
LPC5500
Series
EP GTY x8
QSPI
DSFP28
DSFP28
QSPI Primary
Flash
GTY x4
DDR C1
DDR4 5x16
4/8 GB
x72
Port 1
Port 2
SMBus
PCIe
Gen4 x8
UART
Sensors
A
lv
eo
Co
nf
igur
at
ion Por
t
2xJTAG, 3xUART
PMBus, SMBus, SWDIO
X25588-052622
Terms and Acronyms
The following table lists terms used in the guide and their definitions.
Table 2: Terms and Definitions
Term Definition
AN, AN/LT Auto-negotiation / Link Training.
Sets the speed of an Ethernet link.
ARP Address Resolution Protocol.
Maps IP addresses to MAC addresses.
BASE-R FEC A type of Forward Error Correction also known as Firecode.
CPU Central Processing Unit.
CTPIO Cut Through Programmed Input/Output.
TX packets are streamed directly from the PCIe interface to the adapter port to deliver
lowest TX latency.
DAC cable Direct Attach Copper cable.
DDR Double Data Rate memory.
Transfers data on rising and falling edges of the clock.
DSFP Dual Small Form-factor Pluggable.
A 2-channel (dual) network transceiver design that is compatible with SFP+/ SFP28
transceivers. See https://dsfpmsa.org/ .
Chapter 1: Introduction
UG1523 (v1.0) October 18, 2022 www.xilinx.com
Alveo X3522 User Guide 6
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