Xilinx Alveo X3522, User Manual

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• To view the interrupts that are currently in use, and determine the queues for which they are
being used:
$ cat /proc/interrupts
Note: The example outputs for this command show only the interrupts for a single X3522 interface, and
omit all output related to other devices.
Initially, you see the interrupts for the receive queues (
<interface>-rx-<queue_num>
)
and for the default transmit queue (
<interface>-tx-0
):
$ cat /proc/interrupts
CPU0 CPU1 CPU2 CPU3 CPU4 CPU5 CPU6 CPU7
...
114: 44 0 0 0 1 0 125010 0
PCI-MSI 49283072-edge enp1s0f0np0-rx-0
116: 125010 0 0 0 1 0 44 0
PCI-MSI 49283073-edge enp1s0f0np0-rx-1
118: 58288 44 1 0 0 0 66723 0
PCI-MSI 49283074-edge enp1s0f0np0-rx-2
120: 125010 0 0 0 1 0 0 44
PCI-MSI 49283075-edge enp1s0f0np0-rx-3
122: 0 0 0 0 0 0 0 0
PCI-MSI 49283076-edge enp1s0f0np0-rx-4
124: 0 0 0 0 0 0 0 0
PCI-MSI 49283077-edge enp1s0f0np0-rx-5
126: 0 0 0 0 0 0 0 0
PCI-MSI 49283078-edge enp1s0f0np0-rx-6
128: 0 0 0 0 0 0 0 0
PCI-MSI 49283079-edge enp1s0f0np0-rx-7
130: 18 0 1 0 0 0 31 0
PCI-MSI 49283080-edge enp1s0f0np0-tx-0
...
As applications start, the interrupts for their transmit queues are added to the output (
onld-
<n>
below):
$ cat /proc/interrupts
CPU0 CPU1 CPU2 CPU3 CPU4 CPU5 CPU6 CPU7
...
114: 44 0 0 0 1 0 125010 0
PCI-MSI 49283072-edge enp1s0f0np0-rx-0
116: 125010 0 0 0 1 0 44 0
PCI-MSI 49283073-edge enp1s0f0np0-rx-1
118: 58288 44 1 0 0 0 66723 0
PCI-MSI 49283074-edge enp1s0f0np0-rx-2
120: 125010 0 0 0 1 0 0 44
PCI-MSI 49283075-edge enp1s0f0np0-rx-3
122: 0 0 0 0 0 0 0 0
PCI-MSI 49283076-edge enp1s0f0np0-rx-4
124: 0 0 0 0 0 0 0 0
PCI-MSI 49283077-edge enp1s0f0np0-rx-5
126: 0 0 0 0 0 0 0 0
PCI-MSI 49283078-edge enp1s0f0np0-rx-6
128: 0 0 0 0 0 0 0 0
PCI-MSI 49283079-edge enp1s0f0np0-rx-7
130: 18 0 1 0 0 0 31 0
PCI-MSI 49283080-edge enp1s0f0np0-tx-00
132: 0 0 0 0 0 0 0 0
PCI-MSI 49283081-edge onld-0
133: 0 0 0 0 0 0 0 0
Chapter 5: Tuning
UG1523 (v1.0) October 18, 2022 www.xilinx.com
Alveo X3522 User Guide 31
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