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Production Data

WM8804

PD Rev 4.1 September 2007

REGISTER

ADDRESS

BIT LABEL DEFAULT

DESCRIPTION

5:4 REC_FREQ

[1:0]

Recovered Frequency Flag

Indicates recovered S/PDIF clock frequency:
00 = 192kHz
01 = 96kHz or 88.2kHz
10 = 48kHz or 44.1kHz
11 = 32kHz

6 UNLOCK

Unlock Flag

Indicates that the S/PDIF Rx clock recovery
circuit is unlocked.
0 = Locked onto incoming S/PDIF stream.
1 = Not locked onto the incoming S/PDIF
stream.

0 CON/PRO

Use Of Channel Status Block

0 = Consumer Mode
1 = Professional Mode
The WM8804 is a consumer mode device.
Detection of professional mode may give
erroneous behaviour.

1 AUDIO_N

Linear PCM Identification

0 = Data word represents audio PCM samples.
1 = Data word does not represent audio PCM
samples.

2 CPY_N

Copyright Information

0 = Copyright is asserted for Rx data.
1 = Copyright is not asserted for Rx data.

3 DEEMPH

Additional Format Information

0 = Recovered S/PDIF data has no pre-
emphasis.
1 = Recovered S/PDIF data has pre-emphasis.

5:4

Reserved

Reserved for additional de-emphasis modes.

R13

RXCHAN1

0Dh

(read-only)

7:6 CHSTMODE

[1:0]

Channel Status Mode

00 = Only valid mode for consumer
applications.

R14

RXCHAN2

0Eh

(read-only)

7:0 CATCODE

[7:0]

00000000

Category Code

Refer to S/PDIF specification (IEC 60958-3) for
full details.
0x00h indicates “general” mode.

3:0 SRCNUM

[3:0]

0000

S/PDIF Source Number

Refer to S/PDIF specification (IEC 60958-3) for
full details.

5:4 CHNUM1[1:0]

Channel Number For Sub-frame 1

00 = do not use channel number
01 = channel 1 to left channel
10 = channel 1 to right channel

R15

RXCHAN3

0Fh

(read-only)

7:6 CHNUM2[1:0]

Channel Number For Sub-frame 2

00 = do not use channel number
01 = channel 2 to left channel
10 = channel 2 to right channel

R16

RXCHAN4

3:0 FREQ[3:0]

0001

Indicated Sampling Frequency

Refer to S/PDIF specification (IEC 60958-3) for
full details.

Summary of Contents for WM8804

Page 1: ...trol interface on the GPO pins or streamed over the audio data interface in With Flags mode audio data with status flags appended The audio data interface supports I 2 S left justified right justified...

Page 2: ...O INTERFACE SLAVE MODE 8 CONTROL INTERFACE 3 WIRE MODE 9 CONTROL INTERFACE 2 WIRE MODE 10 DEVICE DESCRIPTION 11 INTRODUCTION 11 POWER UP CONFIGURATION 12 CONTROL INTERFACE OPERATION 14 HARDWARE CONTRO...

Page 3: ...Top View ORDERING INFORMATION DEVICE TEMPERATURE RANGE PACKAGE MOISTURE SENSITIVITY LEVEL PEAK SOLDERING TEMPERATURE WM8804GEDS 25 to 85o C 20 lead SSOP Pb free MSL1 260o C WM8804GEDS R 25 to 85o C 2...

Page 4: ...rol mode or 2 wire software control Mode See note 2 6 RESETB Digital Input System reset active low 7 PVDD Supply PLL core supply 8 PGND Supply PLL ground 9 CLKOUT Digital Out High drive clock output a...

Page 5: ...ure Sensitivity to determine acceptable storage conditions prior to surface mount assembly These levels are MSL1 unlimited floor life at 30 C 85 Relative Humidity Not normally stored in moisture barri...

Page 6: ...3V 14 9 mA PLL supply current IPVDD PVDD 3 3V 1 7 mA Power Consumption DVDD PVDD 3 3V 54 8 mW Standby Power Consumption DVDD PVDD 3 3V Device powered down 0 11 mW ELECTRICAL CHARACTERISTICS Test Cond...

Page 7: ...th low tMLCKL 11 ns MCLK Duty cycle 40 60 60 40 Table 1 Master Clock Timing Requirements DIGITAL AUDIO INTERFACE MASTER MODE BCLK DOUT LRCLK tDL DIN tDDA tDHT tDST Figure 2 Digital Audio Data Timing M...

Page 8: ...stated PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Audio Data Input Timing Information BCLK cycle time tBCY 50 ns BCLK pulse width high tBCH 20 ns BCLK pulse width low tBCL 20 ns LRCLK set up t...

Page 9: ...TYP MAX UNIT Program Register Input Information SCLK rising edge to CSB rising edge tSCS 60 ns SCLK cycle time tSCY 80 ns SCLK duty cycle 40 60 60 40 SDIN to SCLK set up time tDSU 20 ns SDIN hold time...

Page 10: ...ess stated PARAMETER SYMBOL MIN TYP MAX UNIT Program Register Input Information SCLK cycle time tSCY 2500 ns SCLK duty cycle 40 60 60 40 SCLK frequency 400 kHz Hold Time Start Condition tSTHO 600 ns S...

Page 11: ...onfigured to output all standard MCLK frequencies or it can be configured to maintain the frequency of the last received S PDIF data stream The transmitter generates S PDIF frames where audio data may...

Page 12: ...rs Table 6 summarises the configuration options HW RESET 0 HW RESET 1 SWMODE HWMODE SWMODE HWMODE SDIN HWMODE SWMODE Select SDIN N A SCLK N A AIF_MS SCLK GPO TRANS_ERR 2 wire 3 wire SDOUT N A AIF_CONF...

Page 13: ...efault and must be powered up individually by writing to the relevant bits of the PWRDN register Table 7 In hardware control mode all functions of the device are powered up by default REGISTER ADDRESS...

Page 14: ...he GPO0 SWIFMODE pin on power up or at a hardware reset If the GPO0 SWIFMODE pin is low the interface is configured in 2 wire mode otherwise the interface is configured in 3 wire SPI compatible mode G...

Page 15: ...register bits This 3 wire interface read back method using a write access is shown in Figure 9 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 2 0 READMUX 2 0 000 Status Register Select Determines whic...

Page 16: ...ss does not match that of the WM8804 the device returns to the idle condition and waits for a new start condition and valid address Once the WM8804 has acknowledged a matching address the controller s...

Page 17: ...ontroller will issue a repeated start condition and resend the device address along with a read bit The WM8804 will acknowledge this and the WM8804 will become a slave transmitter The WM8804 will tran...

Page 18: ...in either software or hardware control modes The method of control is determined by sampling the state of the SDIN pin during power up or hard reset If SDIN is LOW during power up or hardware reset th...

Page 19: ...e However in hardware control mode both sides of the interface are combined and the configuration is set using SDOUT and GPO0 pins as described in Table 6 and Table 16 Note that AIF_CONF 1 0 configure...

Page 20: ...prior to changing the TXSRC control register and powered up again once the routing path has been changed REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R30 PWRDN 1Eh 2 SPDIFTXPD 1 S PDIF Transmitter P...

Page 21: ...function of the oscillator is to generate the oscillator clock OSCCLK for the PLL input Whenever the PLL or the S PDIF receiver is enabled the oscillator must be used to generate the OSCCLK signal fo...

Page 22: ...ration S PDIF Receive Mode Automatic PLL Mode Selected if S PDIF Receiver Enabled In S PDIF receive mode the PLL is automatically controlled by the S PDIF receiver to allow the receiver to use the PLL...

Page 23: ...8 and K is configured to provide a multiplication factor of 0 192 the overall multiplication factor is 8 0 192 8 192 In order to choose and configure the correct values for PLL_N and PLL_K multiplica...

Page 24: ...ormance when the f2 clock is between 90 and 100MHz The necessary MCLK frequency is 12 288MHz Choose MCLKDIV and FREQMODE values to set the f2 frequency in the range of 90 to 100MHz In this case the de...

Page 25: ...ples When considering settings not shown in this table the key configuration parameters which must be selected for optimum operation are 90MHz f2 100MHz 5 PLL_N 13 OSCCLOCK 10 to 14 4MHz or 16 28 to 2...

Page 26: ...OR F2 TO CLK2 DIVISION FACTOR CLKOUTDIV 1 0 MCLKDIV FREQMODE 1 0 00 01 10 11 0 1 00 2 2 4 8 2 4 01 2 4 8 16 4 8 10 4 8 16 32 8 16 11 6 12 24 48 12 24 Table 27 PLL User Mode Clock Divider Configuration...

Page 27: ...ta SPDIFTXCLK Source MCLK Input Output Signal at MCLK Pin Table 30 S PDIF Transmitter Data MCLK Source Control The S PDIF transmitter requires a clock reference signal either CLK2 or MCLK when enabled...

Page 28: ...Configuration section for details regarding how to calculate alternative settings OSC CLK MHz PRE SCALE S PDIF RECEIVER SAMPLE RATE S kHz F1 MHz F2 MHz R PLL_N Hex PLL_K Hex COMMENT 11 2896 0 32 44 1...

Page 29: ...y different The setting up of these different configurations are described in the following paragraphs 176 4KHZ OR 192K MODE ENABLE The difference between a sample rate of 176 4kHz and 192kHz requires...

Page 30: ...be used Note also that the SPD_192K_EN register bit is set by default thus supporting 192kHz sampling rate The clock source for the S PDIF transmitter is selected by TXSRC which is latched from the C...

Page 31: ...0 is defined by TXVAL_SF0 validity bit transmitted for subframe 1 is defined by TXVAL_SF1 6 TXSRC 1 S PDIF Transmitter Data Source 0 S PDIF received data 1 Audio interface received data R21 SPDTX4 15...

Page 32: ...ty for data as a means of basic error detection It is generated by the transmitter REGISTER ADDRESS BIT LABEL CHANNEL STATUS BIT DEFAULT DESCRIPTION 0 CON PRO 0 0 Use Of Channel Status Block 0 Consume...

Page 33: ...Function 00 Do not use channel number 01 Send to Left Channel 10 Send to Right Channel R20 SPDTX3 14h 7 6 CHNUM2 1 0 21 20 23 22 00 11 Do not use channel number Table 36 S PDIF Transmitter Channel St...

Page 34: ...EIVER The S PDIF receiver has one input This input can be configured as either single ended CMOS or as a 500mVp p comparator input depending upon the state of the SPDIFINMODE register The S PDIF recei...

Page 35: ...cation using the WL_MASK In this case all 24 bits of data received are transferred The audio data sample can be transferred to either the AIF or the SPDIF Tx When the audio data sample is transferred...

Page 36: ...7 6 CHSTMODE 1 0 7 6 00 Channel Status Mode 00 Only valid mode for consumer applications Table 40 S PDIF Receiver Channel Status Register 1 REGISTER ADDRESS BIT LABEL CHANNEL STATUS BIT DEFAULT DESCR...

Page 37: ...ption of bits 3 1 of this register Audio Sample Word Length 000 Word length not indicated RXWL 2 0 MAXWL 1 MAXWL 0 001 20 bits 16 bits 010 22 bits 18 bits 100 23 bits 19 bits 101 24 bits 20 bits 110 2...

Page 38: ...egister PCM_N Non PCM Flag Indicates that non audio code defined in IEC 61937 has been detected 0 Sync code not detected 1 Sync code detected received data is not audio PCM S PDIF Status Register ZERO...

Page 39: ...med transmitted from the digital audio interface When WITHFLAG is set to 1 With Flags mode is enabled and the flags in Table 47 are appended to the LSB of the audio sample If WITHFLAG is set to 0 With...

Page 40: ...in asserted until they are cleared by reading the Interrupt Status Register REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0 UPD_UNLOCK UNLOCK update signal 0 INT_N not caused by a toggle of UNLOCK fl...

Page 41: ...ecovered Frequency Flag Indicates recovered S PDIF clock frequency 00 192kHz 01 96kHz or 88 2kHz 10 48kHz or 44 1kHz 11 32kHz R12 SPDSTAT 0Ch read only 6 UNLOCK Unlock Flag Indicates that the S PDIF R...

Page 42: ...ation processor is not being interrupted via the INT_N signal leaving the WM8804 to handle the error condition If the TRANS_ERR and INVALID error flags are masked using the MASK register the WM8804 ou...

Page 43: ...ad does not contain audio PCM data NON_AUDIO data is indicated by a logical OR of the AUDIO_N and PCM_N flags Any change of AUDIO_N or PCM_N status will cause an INT_N interrupt UPD_NON_AUDIO to be ge...

Page 44: ...e Table 56 In master mode AIF_MS 1 LRCLK and BCLK are generated by the WM8804 As in slave mode DIN is sampled on the rising edge of BCLK and DOUT changes on the falling edge of BCLK and the polarity o...

Page 45: ...gh for a minimum of n BCLKs and low for a minimum of n BCLKs where n is the number of bits in an audio word Any mark to space ratio on LRCLK is acceptable provided the above requirements are met The d...

Page 46: ...LEFT CHANNEL RIGHT CHANNEL LRCLK BCLK DIN DOUT 1 fs n 3 2 1 n 2 n 1 LSB MSB n 3 2 1 n 2 n 1 LSB MSB Figure 19 Right Justified Mode I 2 S MODE In I2 S Mode the MSB of DIN is sampled by the WM8804 on t...

Page 47: ...ata Figure 21 LRCLK BCLK DIN DOUT Input Word Length IWL 1 fs LEFT n 2 1 n 1 LSB MSB n 2 1 n 1 RIGHT NO VALID DATA 1 BCLK 1 BCLK Figure 21 DSP Mode A DSP MODE B In DSP Mode B the MSB of the left channe...

Page 48: ...status flags within the audio sample for each audio data format when With Flags Mode is enabled With Flags Mode is only available on pin DOUT The WM8804 does not support Right Justified 24 Bit With F...

Page 49: ...Production Data WM8804 w PD Rev 4 1 September 2007 49 Figure 26 DSP Mode A With Flags Figure 27 DSP Mode B With Flags...

Page 50: ...ight justified mode 3 2 AIFTX_WL 1 0 01 Audio Data Word Length 11 24 bits see notes 1 2 3 6 10 24 bits see notes 1 2 3 6 01 20 bits 00 16 bits 4 AIFTX_BCP 0 BCLK invert for master and slave modes 0 BC...

Page 51: ...exactly 32 BCLK cycles occur in one LRCLK 16 high 16 low the chip will auto detect and operate in 16 bit data word length mode Note 3 24 bit Right Justified With Flags Mode is not supported Note 4 Mus...

Page 52: ...LKOUTSRC 0 0 0 00011000 R9 SPDMODE 09 1 1 1 1 1 1 1 SPDIFINMODE 11111111 R10 INTMASK 0A MASK 7 0 00000000 R11 INTSTAT 0B Interrupt Status read only R12 SPDSTAT 0C S PDIF Status read only R13 RXCHAN1 0...

Page 53: ...N 3 0 0111 Integer N part of PLL frequency ratio R Use values in the range 5 PLL_N 13 as close as possible to 8 Note PLL_N must be set to specific values when the S PDIF receiver is used Refer to S PD...

Page 54: ...r MCLKDIV configuration in PLL user mode See Table 28 for MCLKDIV configuration in PLL S PDIF receive mode 5 4 CLKOUTDIV 1 0 01 CLKOUT Divider Select Only valid when CLK1 is selected as CLKOUT output...

Page 55: ...F specification IEC 60958 3 for full details R10 INTMASK 0Ah 7 0 MASK 7 0 00000000 Interrupt Mask Enable When a flag is masked it does not update the Interrupt Status Register or cause an INT_N interr...

Page 56: ...toggle of CPY_N flag 1 INT_N caused a toggle of CPY_N flag 6 UPD_DEEMPH DEEMPH Update Signal 0 INT_N not caused by a toggle of DEEMPH flag 1 INT_N caused by a toggle of DEEMPH flag R11 INTSTAT 0Bh rea...

Page 57: ...is not asserted for Rx data 3 DEEMPH 0 Additional Format Information 0 Recovered S PDIF data has no pre emphasis 1 Recovered S PDIF data has pre emphasis 5 4 Reserved 00 Reserved for additional de emp...

Page 58: ...3 0 0000 Original Sampling Frequency Refer to S PDIF specification IEC 60958 3 for full details 0 CON PRO 0 Use Of Channel Status Block 0 Consumer Mode 1 Professional Mode not supported by WM8804 1 A...

Page 59: ...CLKACU 1 0 11 Clock Accuracy of Transmitted Clock 00 Level II 01 Level I 10 Level III 11 Interface frame rate not matched to sampling frequency 6 TXSRC 1 S PDIF Transmitter Data Source 0 S PDIF Receiv...

Page 60: ...mode 10 I2 S mode 01 Left justified mode 00 Right justified mode 3 2 AIFTX_WL 1 0 01 Audio Data Word Length Select 11 24 bits 10 24 bits 01 20 bits 00 16 bits 4 AIFTX_BCP 0 BCLK Invert for master and...

Page 61: ...nel Status Register 2 011 Channel Status Register 3 100 Channel Status Register 4 101 Channel Status Register 5 110 S PDIF Status Register 3 CONT 0 Continuous Read Enable 0 Continuous read back mode d...

Page 62: ...Powerdown 0 S PDIF receiver enabled 1 S PDIF receiver disabled 2 SPDIFTXPD 1 S PDIF Transmitter Powerdown 0 S PDIF transmitter enabled 1 S PDIF transmitter disabled 3 OSCPD 0 Oscillator Power down 0...

Page 63: ...Production Data WM8804 w PD Rev 4 1 September 2007 63 APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 28 Recommended External Components for Hardware Control Mode...

Page 64: ...WM8804 Production Data w PD Rev 4 1 September 2007 64 Figure 29 Recommended External Components for Software Control Mode...

Page 65: ...XCEED 0 20MM D MEETS JEDEC 95 MO 150 VARIATION AE REFER TO THIS SPECIFICATION FOR FURTHER DETAILS DM0015 C DS 20 PIN SSOP 7 2 x 5 3 x 1 75 mm Symbols Dimensions mm MIN NOM MAX A 2 0 A1 0 05 A2 1 65 1...

Page 66: ...ms where malfunction can reasonably be expected to result in personal injury death or severe property or environmental damage Any use of products by the customer for such purposes is at the customer s...

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