WM8804
Production Data
w
PD Rev 4.1 September 2007
16
Figure 10 3-Wire Control Interface Read-Back Method 2
2-WIRE SERIAL CONTROL MODE - REGISTER WRITE
The WM8804 supports software control via a 2-wire serial bus. Many devices can be controlled by
the same bus and each device has a unique 7-bit address (see Table 11).
The controller indicates the start of data transfer with a high to low transition on SDIN while SCLK
remains high. This indicates that a device address, DEVA(7:1), and data, REG(6:0), will follow. All
devices on the 2-wire bus will shift in the next eight bits on SDIN (7-bit address DEVA(7:1), +
read/write ‘W’ bit, MSB first). If the device address received matches the address of the WM8804,
the WM8804 responds by driving SDIN low on the next clock pulse (ACK). This is a device
acknowledgement of an address match. If the address does not match that of the WM8804, the
device returns to the idle condition and waits for a new start condition and valid address.
Once the WM8804 has acknowledged a matching address, the controller sends the first byte of
control data, which is the WM8804 register address (REGA[6:0]). The WM8804 then acknowledges
reception of the control data byte by pulling SDIN low for one clock pulse (another ACK). The
controller then sends the second byte of control data (DIN[7:0], i.e. the eight bits of register data to
be written), and the WM8804 acknowledges again by pulling SDIN low (another ACK).
The transfer of data is complete when there is a low to high transition on SDIN while SCLK is high.
After receiving a complete address and data sequence the WM8804 returns to the idle state and
waits for another start condition. If a start or stop condition is detected out of sequence at any point
during data transfer (i.e. SDIN changes while SCLK is high), the device returns to the idle condition.
Figure 11 2-Wire Serial Control Interface Write
