Production Data
WM8804
w
PD Rev 4.1 September 2007
53
REGISTER
ADDRESS
BIT LABEL DEFAULT
DESCRIPTION
R00
RST/DEVID1
00h
7:0
RESET
-
Writing to this register will apply a reset to the
device.
Reading from this register will return the
second part of the device ID
00000101 = 05h
R01
DEVID2
01h
(read only)
7:0 DEVID2 10001000
Reading from this register will return the first
part of the device ID
10001000 = 88h
R02
DEVREV
02h
3:0 DEVREV[3:0]
-
R3
PLL1
03h
7:0 PLL_K[7:0] 00100001
R4
PLL2
04h
7:0 PLL_K[15:8] 11111101
R5
PLL3
05h
5:0 PLL_K[21:16] 00110110
Fractional (K) part of PLL frequency ratio (R).
Value K is one 22-digit binary number spread
over registers R3, R4 and R5 as shown.
Note: PLL_K must be set to specific values
when the S/PDIF receiver is used. Refer to
S/PDIF Receiver clocking section for
details.
3:0
PLL_N[3:0]
0111
Integer (N) part of PLL frequency ratio (R).
Use values in the range 5
≤
PLL_N
≤
13 as
close as possible to 8
Note: PLL_N must be set to specific values
when the S/PDIF receiver is used. Refer to
S/PDIF Receiver clocking section for
details.
4 PRESCALE
0
PLL Pre-scale Divider Select
0 = Divide by 1 (PLL input clock = oscillator
clock)
1 = Divide by 2 (PLL input clock = oscillator
clock
÷
2)
5 TXVAL_SF0
0
Overwrite Mode S/PDIF Transmitter Validity
Sub-Frame 0
0 = transmit validity = 0
1 = transmit validity = 1
6 TXVAL_SF1
0
Overwrite Mode S/PDIF Transmitter Validity
Sub-Frame 1
0 = transmit validity = 0
1 = transmit validity = 1
R6
PLL4
06h
7 TXVAL_
OVWR
0
S/PDIF Transmitter Validity Overwrite Mode
Enable
0 = disabled, validity bit is 0 when the S/PDIF
transmitter sources PCM audio interface, or it
matches the S/PDIF input validity when the
S/PDIF transmitter sources the S/PDIF
receiver.
1 = enabled, validity bit transmitted for
subframe 0 is defined by TXVAL_SF0, validity
bit transmitted for subframe 1 is defined by
TXVAL_SF1.
