WM8804
Production Data
w
PD Rev 4.1 September 2007
4
PIN DESCRIPTION
PIN
NAME
TYPE
DESCRIPTION
1
SCLK
Digital In/Out
Control interface clock / GPO in hardware control mode. See note 2.
2
GPO0 / SWIFMODE
Digital In/Out
General purpose digital output or selected functionality at hardware reset.
See note 2.
3
SDIN / HWMODE
Digital Input
Control interface data input and hardware/software mode select at hardware
reset. See note 2.
4
SDOUT / GPO2
Digital In/Out
Control interface data output in 3-wire software control mode/ GPO in
hardware control mode or 2-wire software control mode. See note 2.
5
CSB / GPO1
Digital In/Out
Chip select / GPO in hardware control mode or 2-wire software control
Mode. See note 2
6
RESETB
Digital Input
System reset (active low)
7
PVDD
Supply
PLL core supply
8 PGND Supply
PLL
ground
9
CLKOUT
Digital Out
High drive clock output at 64fs, 128fs, 256fs and 512fs
10 XOP
Digital
Output
Crystal
output
11 XIN
Digital
Input
Crystal
input
12
DOUT
Digital Out
Audio interface data output
13
DIN
Digital In
Audio interface data input
14
BCLK
Digital In/Out
Audio interface bit clock
15
LRCLK
Digital In/Out
Audio interface left/right word clock
16
MCLK
Digital In/Out
Master clock input or output
17
TX0
Digital Out
S/PDIF transmit channel
18 DGND Supply
Digital
ground
19
DVDD
Supply
Digital core supply
20
RX0
Digital In
S/PDIF receive channel
Notes
:
1.
Digital input pins have Schmitt trigger input buffers.
2. Refer to Table 6 Device Configuration at Power up or Hardware Reset
