F2 ULV-CPU
50
POST Code
(Hex)
Name
Description
22h
8742_TEST
Read 8742 self-test results.
IF <self-test failed> THEN
Halt.
ELSE
Read system info from 8742
Set 8742 command byte.
ENDIF
24h
SET_HUGE_ES
Go into protected mode.
Set ES, DS, SS, FS, and GS to 4Gb.
28h
SIZE_RAM
Determine the size of each DRAM bank. Set DRAM con-
troller configuration registers to enable DRAM.
29h
MEM_MGR_INIT
Initialize the POST Memory manager.
2Ah
ZERO_BASE_RAM
Clear the 512k of DRAM.
2Ch
ADDR_TEST
Test for stuck address line in lower 1M of address space,
IF <test failed> THEN
Halt.
ENDIF
2Eh
BASERAML
Test for stuck DRAM data line by walking a 1 through all
bit locations of address 0 and then walking a 0 through.
IF <test failed> THEN
Halt.
ENDIF
2Fh
PRE_SYS_SHADOW
Clears the cache before shadowing the system.
32h
COMPUTE_SPEED
Determine the CPU core speed by timing the execution
of a loop.
33h
PDM_INIT
Initialize the Phoenix Dispatch Manager.
34h
CMOS_TEST
Clear CMOS diagnostic byte.
IF <CMOS battery is dead> THEN
Set “bad battery” flag in CMOS
IF <CMOS checksum is bad> THEN
Set “bad CMOS check” flag in CMOS
Checksum CMOS
ENDIF
ENDIF
36h
CHK_SHUTDOWN
Vector to proper shutdown routine (reset).
38h
SYS_SHADOW
Copy system BIOS ROM to shadow RAM.
3Ah
CACHE_AUTO
Detect the amount of SRAM for the L2 cache. Set L2
cache controller configuration registers to enable SRAM.