F2 ULV-CPU
12
five general purpose inputs, register based block locking and hardware based locking.
It operates under the LPC/FWH interface protocol.
The Firmware Hub is housed in a 32pin PLCC.
Super I/O-Controller
The PC87366 is a Low Pin Count Interface-based highly integrated Super I/O and provides
the following functions:
Two 16C550 UARTs
IEEE1284 Parallel Port
Floppy Disk Controller
Keyboard and PS/2 Mouse Controller
Enhanced Hardware Monitor
Fan Speed Controller
40 General Purpose I/O pins
Intrusion sensor logic
The PC87366 is housed in a 128 pin QFP package.
PCI Serial Port Controller
The IT8874F provides a simple solution to build a serial port on PCI bus. The controller
integrates two serial ports based on 16C550 UART function.
The IT8874F is housed in a 128 pin PQFP package.
Chrystalclear Sound fusion Audio Codec `97
The CS4299 is a Codec with AC´97 features. It is implemented as 20 bit stereo DAC and 18
bit stereo ADC with sample rate conversion. The F2- CPU uses one microphone mono input
and the line stereo output which will drive the stereo amplifier TEA2025B.
The CS4299 is housed in a 48 pin LQFP package.
Stereo Amplifier
The TEA2025B is a stereo audio power amplifier capable of delivering typically 1.25 Watt per
channel of continuous average power to an 8 Ohm load with 0.1% (THD) using a 12 V power
supply. The TEA2025B is housed in a 16 pin DIL package.
Clock Generator
The ICS Clock Generator ICS954204 is designed for the INTEL “Alviso” chipset and provides
all clocks for the chipset, microprocessor, PCI interface, SATA interface, USB interface and
Super I/O. The RAM clocks are provided by the GMCH.
