Wincor Nixdorf BEETLE F2-ULV-CPU, User Manual

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F2 ULV-CPU
49
POST Code
(Hex)
Name Description
02h VERIFY_REAL IF <in port mode> THEN
Turn on A20
Reset Processor
ENDIF
03h DISABLE_NMI Disable non-maskable Interrupts
04h GET_CPU_TYPE IF <cold boot> THEN
Store reset DX value in CMOS
Determine CPU manufacturer and type
Store CPU manufacturer and type in CMOS
ENDIF
06h HW_INIT Reset all DMA controllers.
Disable all video controllers.
Clear any pending interrupts from the RTC
Set up port 61h to speaker off and timer gate enabled.
08h CS_INIT Set DRAM controller registers to values that are needed
for DRAM discovery and testing.
09h SET_IN_POST Set bit in CMOS indicating that POST is in progress.
Not cleared until Post Code Aeh.
0Ah CPU_INIT Set CPU configuration registers.
0Bh CPU_CACHE_ON Turns on the CPU cache.
0Ch CACHE_INIT Set L2 cache controller registers to values needed for
SRAM discovery and testing.
0Eh IO_INIT IF <onboard super I/O exists> THEN
Turn Off LPT and COM ports in super I/O.
Set I/O controller registers to default values.
ENDIF
0Fh FDISK_INIT IF <secondary IDE controllers exists> THEN
Set secondary IDE controller configura-
tion registers to default values.
ENDIF
10h PM_INIT IF <power management enabled> THEN
Set the power management configuration registers
to default values.
ENDIF
11h REG_INIT Set Cx5520 configuration registers to default values.
Set any other configuration registers to default values.
12h RESTORE_CR0 Return to real mode.
13h PCI_BM_RESET Early reset of PCI devices required to disable bus mas-
ters. Assumes the presence of a stack and running from
decompressed shadow memory.
14h 8742_INIT Verify 8742 (keyboard controller) is responding. Improper
connections/timing to the 8742. Send self test command
to 8742.
16h CHECKSUM Checksum the system BIOS ROM
IF <checksum is incorrect> THEN
Halt.
ENDIF
17h PRE_SIZE_RAM Initialize external cache before autosizing memory.
18h TIMER_INIT Initialize all three of the 8254 timers.
1Ah DMA_INIT Initialize the DMA command register and all 8 DMA
channels.
1Ch RESET_PIC Initialize the 8259 interrupt controller.
20h REFRESH Copy test code to RAM and execute that code looking
for refresh bit in port 61h to toggle.
IF <refresh test failed> THEN
Halt.
ENDIF