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W78C438C

Publication Release Date: July 1998

- 15 -

Revision A1

CRYSTAL

C1

C2

R

16 MHz

30P

30P

24 MHz

15P

15P

33 MHz

10P

10P

6.8K

40 MHz

5P

5P

6.8K

    Above table shows the reference values for crystal applications.

Notes:
1. For C1, C2, R components refer to Figure A.
2. It is recommended that the crystals be replaced with oscillators for applications above 35 MHz.

PACKAGE DIMENSIONS

84-pin PLCC

2

A

H

D

D

e

b

E H

E

y

A

A

Seating Plane

D

G

E

11

84

75

1

12

32

33

53

54

74

Symbol

Min. Nom. Max.

Max.

Nom.

Min.

Dimension in inches

Dimension in mm

A

b
c
D

e

H

E

L
y

A
A

1

2

E

b

1

H

D

G

G

D

E

0.020

0.143

0.026

0.016

0.006

1.148

1.095

1.180

0.090

0.148

0.028

0.018

0.008

1.153

1.115

1.190

0.100

0.050

0.185

0.153

0.032

0.022

0.012

1.158

1.135

1.200

0.110

0.004

0.51

3.63

0.66

0.41

0.15

29.17

27.81

29.98

2.29

3.76

0.71

0.46

0.20

29.29

28.32

30.23

2.54

1.27

4.70

3.89

0.81

0.56

0.30

29.41

28.83

30.48

2.79

0.10

0.044

0.056

1.12

1.42

29.41

29.29

29.17

1.158

1.153

1.148

28.83

28.32

27.81

1.135

1.115

1.095

0

10

10

0

30.48

30.23

29.98

1.200

1.190

1.180

θ

on final visual inspection spec.

4. General appearance spec. should be based

3. Controlling dimension: Inches

protrusion/intrusion.

2. Dimension b1 does not include dambar

flash.

1. Dimension D & E do not include interlead

Notes:

Summary of Contents for W78C438C

Page 1: ...ses The W78C438C also provides four pins AP7 0 AP7 3 to support either 64 KB program 1 MB data memory space or memory mapped chip select logic one parallel I O port Port 8 without bit addressing mode...

Page 2: ...T1 P3 5 P 2 2 32 31 5 6 7 1 2 3 4 8 4 8 0 8 1 8 2 8 3 7 6 7 7 7 8 7 9 P 0 0 P 0 1 P 0 2 P 0 3 D P 4 1 D P 4 0 N C V D D N C D P 4 2 D P 4 3 D P 4 4 D P 4 5 D P 4 6 D P 4 7 P 1 0 P 1 1 P 1 2 P 1 3 P 1...

Page 3: ...0 3 P 0 1 P 0 2 P 0 0 D P 4 0 D P 4 1 D P 4 2 D P 4 3 D P 4 4 D P 4 5 D P 4 6 D P 4 7 T 2 P 1 0 P 1 2 P 1 3 P 1 4 N C NC NC NC NC P2 4 P2 5 P2 7 P2 6 V AP5 7 AP5 6 AP5 5 AP5 4 ALE AP5 0 PSEN AP5 1 P0...

Page 4: ...multiplexed with the 15 8 address of the external data RAM During the execution of MOVX Ri the output of AP6 comes from the HB register which is the page register for the high byte address and its add...

Page 5: ...except that the functions status of these interrupts are determined shown by the bits in the XICON External Interrupt Control register The XICON register is bit addressable but is not a standard regi...

Page 6: ...gram data memory addresses up to 64 KB 1 MB for applications which need additional external memory to store large amounts of data Although there is 1M bytes memory space instructions stored here can n...

Page 7: ...or glue logic These pins are decoded by AP6 7 6 Only one pin is active low at any time That is they are active individually with 16K address resolution For example CS0 is active low in the address ran...

Page 8: ...e The P8 register is not a standard register in the standard W78C32 Its address is at 0A6H To read write the P8 register one can use the MOV direct instruction or read modify write instructions Exampl...

Page 9: ...software Table 2 Functions of XICON Register INTERRUPT SOURCE VECTOR ADDRESS PRIORITY SEQUENCE External Interrupt 0 03H 0 Highest Timer Counter 0 0BH 1 External Interrupt 1 13H 2 Timer Counter 1 1BH...

Page 10: ...ion To support address paging there is an additional 8 bit SFR HB high byte which is a nonstandard register at address 0A1H During execution of the MOVX Ri instruction the contents of HB are output to...

Page 11: ...e VOH1 IOH1 100 A Port 1 2 3 8 2 4 V Output Low Voltage VOL2 IOL2 4mA Note 3 ALE PSEN P0 DP4 0 45 V Output High Voltage VOH2 IOH2 400 A Note 3 ALE PSEN P0 DP4 2 4 V Output Low Voltage VOL3 IOL2 2 mA A...

Page 12: ...he clock may be stopped indefinitely in either state 2 The TCP specification is used as a reference in other specifications 3 There are no duty cycle requirements on the XTAL1 input Program Fetch Cycl...

Page 13: ...AP6 7 0 AP5 7 0 DP4 7 0 address code address TAPL TPDV Data Memory Read Write Cycle S1 S2 S3 S8 S9 S10 S11 S12 S4 S5 S6 S7 XTAL1 PSEN data addr RD DP4 7 0 WR DP4 7 0 DATA OUT addr addr TRS TARL TRDV...

Page 14: ...5 A X T L 1 X T A L 2 5 V 8 2 K 10 U C2 C1 R P1 6 P1 7 RESET P8 1 P8 2 P8 3 P8 4 P8 5 P3 0 RXD P3 1 TXD P3 3 INT1 P3 4 T0 INT3 P3 2 INT0 P3 5 T1 P3 6 WR INT2 P8 0 P8 6 P8 7 A P 7 3 C S 3 A P 7 2 C S 2...

Page 15: ...n mm A b c D e HE L y A A 1 2 E b 1 HD G GD E 0 020 0 143 0 026 0 016 0 006 1 148 1 095 1 180 0 090 0 148 0 028 0 018 0 008 1 153 1 115 1 190 0 100 0 050 0 185 0 153 0 032 0 022 0 012 1 158 1 135 1 20...

Page 16: ...Notes Symbol Min Nom Max Max Nom Min Dimension in inches Dimension in mm A b c D e HD HE L y A A L 1 1 2 E 0 012 0 006 0 152 0 305 24 49 24 80 25 10 12 0 020 0 087 0 032 0 103 0 498 0 802 2 21 2 616...

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