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W78C438C

- 6 -

FUNCTIONAL DESCRIPTION

The W78C438C is a functional extension of the W78C58 microcontroller. It contains a 256 

×

 8 RAM,

64 KB program/1 MB data memory address or memory-mapped chip select logic, two 8-bit address
ports, one 8-bit data port, five general I/O ports, four external interrupts, three timers/counters, and
one serial port.

Dedicated Data and Address Port

The W78C438C provides four general-purpose I/O ports for W78C32 applications; the address and
data bus are separated from Port 0 and Port 2 so that these ports can be used as general-purpose I/O
ports. In this product, DP4 is the data bus for external ROM and RAM, AP5<7:0> are the low byte
address, AP6<7:0> are the high byte address, PSEN enables the external ROM to DP4, and P3.6

(

WR

) and P3.7 (

RD

) are the write/read control signals for the external RAM. The external latch for

multiplexing the low byte address is no longer needed in this product. The W78C438C uses AP5 and
AP6 to support 64 KB external program memory and 64 KB external data memory, just as a standard
W78C32 does.

The W78C438C provides four pins, AP7.3

AP7.0 (CS3

CS0), to support either 64 KB program/1 MB

data memory space or memory-mapped chip select logic. Bit 7 of the EPMA (Extended Program
Memory Address) register, which is described in Table 1 below, determines the functions of these
pins.

When this bit is "0" (the default value), AP7<3:0> support external program/data memory addresses
up to 64 KB/1 MB for applications which need additional external memory to store large amounts of
data.

Although there is 1M bytes memory space, instructions stored here can not be run at full range of this
area except the first 64 Kbytes. It is owing to the fact that during the instruction fetch cycle, AP7<3:0>
always output 0s to address lines A19

A16. This limits the program code to store at address 0

0FFFFH (64K). The rest of the area (10000H

FFFFFH) can be treated as ROM data storage which

can be read by "MOVC A, @A+DPTR" instruction.

When "MOVC A, @A+DPTR" is executed to read the external ROM data or "MOVX dest, src" is
executed to access the external RAM data, AP7<3:0> output address <19:16> from bits <3:0> of the
EPMA (Extended Program Memory Address) register. At other times, AP7<3:0> always output 0H to
ensure the instruction fetch is within the 64K program memory address. Different banks can be
selected by modifying the content of the EPMA register before the execution of "MOVC A,
@A+DPTR" or "MOVX dest, src."

[Example]. Access the external ROM/RAM data from external memory space.

CLR

A

; Clear Accumulator.

MOV

DPTR, #0H

; Clear DPTR.

MOV

0A2H, #02

; Initialize EPMA(0A2H). EPMA.7 = 0: extended memory space

; EPMA.<3:0> = 0010B,  the address range: 20000

2FFFFH.

MOVC

A, @A+DPTR ; Read the external ROM data from location 20000H.

MOVX

A, @DPTR

; Read the external RAM data from location 20000H.

CLR

A

MOV

0A2H, #03H

; EPMA.<3:0> = 0011B, the address range: 30000H

3FFFFH.

MOVC

A, @A+DPTR  ; Read the external ROM data from location 30000H.

MOVX

@DPTR, A

; Write the contents of Accumulator to external RAM data.
; location 30000H. 

Summary of Contents for W78C438C

Page 1: ...ses The W78C438C also provides four pins AP7 0 AP7 3 to support either 64 KB program 1 MB data memory space or memory mapped chip select logic one parallel I O port Port 8 without bit addressing mode...

Page 2: ...T1 P3 5 P 2 2 32 31 5 6 7 1 2 3 4 8 4 8 0 8 1 8 2 8 3 7 6 7 7 7 8 7 9 P 0 0 P 0 1 P 0 2 P 0 3 D P 4 1 D P 4 0 N C V D D N C D P 4 2 D P 4 3 D P 4 4 D P 4 5 D P 4 6 D P 4 7 P 1 0 P 1 1 P 1 2 P 1 3 P 1...

Page 3: ...0 3 P 0 1 P 0 2 P 0 0 D P 4 0 D P 4 1 D P 4 2 D P 4 3 D P 4 4 D P 4 5 D P 4 6 D P 4 7 T 2 P 1 0 P 1 2 P 1 3 P 1 4 N C NC NC NC NC P2 4 P2 5 P2 7 P2 6 V AP5 7 AP5 6 AP5 5 AP5 4 ALE AP5 0 PSEN AP5 1 P0...

Page 4: ...multiplexed with the 15 8 address of the external data RAM During the execution of MOVX Ri the output of AP6 comes from the HB register which is the page register for the high byte address and its add...

Page 5: ...except that the functions status of these interrupts are determined shown by the bits in the XICON External Interrupt Control register The XICON register is bit addressable but is not a standard regi...

Page 6: ...gram data memory addresses up to 64 KB 1 MB for applications which need additional external memory to store large amounts of data Although there is 1M bytes memory space instructions stored here can n...

Page 7: ...or glue logic These pins are decoded by AP6 7 6 Only one pin is active low at any time That is they are active individually with 16K address resolution For example CS0 is active low in the address ran...

Page 8: ...e The P8 register is not a standard register in the standard W78C32 Its address is at 0A6H To read write the P8 register one can use the MOV direct instruction or read modify write instructions Exampl...

Page 9: ...software Table 2 Functions of XICON Register INTERRUPT SOURCE VECTOR ADDRESS PRIORITY SEQUENCE External Interrupt 0 03H 0 Highest Timer Counter 0 0BH 1 External Interrupt 1 13H 2 Timer Counter 1 1BH...

Page 10: ...ion To support address paging there is an additional 8 bit SFR HB high byte which is a nonstandard register at address 0A1H During execution of the MOVX Ri instruction the contents of HB are output to...

Page 11: ...e VOH1 IOH1 100 A Port 1 2 3 8 2 4 V Output Low Voltage VOL2 IOL2 4mA Note 3 ALE PSEN P0 DP4 0 45 V Output High Voltage VOH2 IOH2 400 A Note 3 ALE PSEN P0 DP4 2 4 V Output Low Voltage VOL3 IOL2 2 mA A...

Page 12: ...he clock may be stopped indefinitely in either state 2 The TCP specification is used as a reference in other specifications 3 There are no duty cycle requirements on the XTAL1 input Program Fetch Cycl...

Page 13: ...AP6 7 0 AP5 7 0 DP4 7 0 address code address TAPL TPDV Data Memory Read Write Cycle S1 S2 S3 S8 S9 S10 S11 S12 S4 S5 S6 S7 XTAL1 PSEN data addr RD DP4 7 0 WR DP4 7 0 DATA OUT addr addr TRS TARL TRDV...

Page 14: ...5 A X T L 1 X T A L 2 5 V 8 2 K 10 U C2 C1 R P1 6 P1 7 RESET P8 1 P8 2 P8 3 P8 4 P8 5 P3 0 RXD P3 1 TXD P3 3 INT1 P3 4 T0 INT3 P3 2 INT0 P3 5 T1 P3 6 WR INT2 P8 0 P8 6 P8 7 A P 7 3 C S 3 A P 7 2 C S 2...

Page 15: ...n mm A b c D e HE L y A A 1 2 E b 1 HD G GD E 0 020 0 143 0 026 0 016 0 006 1 148 1 095 1 180 0 090 0 148 0 028 0 018 0 008 1 153 1 115 1 190 0 100 0 050 0 185 0 153 0 032 0 022 0 012 1 158 1 135 1 20...

Page 16: ...Notes Symbol Min Nom Max Max Nom Min Dimension in inches Dimension in mm A b c D e HD HE L y A A L 1 1 2 E 0 012 0 006 0 152 0 305 24 49 24 80 25 10 12 0 020 0 087 0 032 0 103 0 498 0 802 2 21 2 616...

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