W78C438C
Publication Release Date: July 1998
- 13 -
Revision A1
TIMING WAVEFORMS
Program Fetch Cycle
S1
S2
XTAL1
PSEN
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
AP6<7:0>
AP5<7:0>
DP4<7:0>
address
code
address
T
APL
T
PDV
Data Memory Read/Write Cycle
S1
S2
S3
S8
S9
S10
S11
S12
S4
S5
S6
S7
XTAL1
PSEN
data
addr.
RD
DP4<7:0>
WR
DP4<7:0>
DATA OUT
addr.
addr.
T
RS
T
ARL
T
RDV
T
RDQ
T
WS
T
DWL
T
WDQ
T
AWL
AP6<7:0>
DPH or HB SFR out
PGM address
PGM address
DPL or Ri out
AP5<7:0>
AP7<3:0>
addr <19:16> out
(When bit7 of EPMA is 0.)