VTI Instruments EX1401, User Manual

Page: 20 / 114

VTI Instruments Corp.
20 EX1401 Introduction
DIO S
PECIFICATIONS
N
UMBER OF
DIO
CHANNELS
8
E
LECTRICAL
S
PECIFICATIONS
Maximum Input Voltage
Input Impedance
Minimum Input Pulse Width
Minimum Output Pulse Width
V
IL
V
IH
V
OL
V
OH
I
MAX
-0.5V to 5.5V, ESD protected
Signal is pulled low by a 10k Ohm resistor
100 μs
100 μs, updated synchronously with the ADC sampling, prior to decimation
< 0.8V
> 2.0V
< 0.55V @ 10 mA
> 2.0 V @ 10 mA
10mA max per channel, 20mA max per bank
I
SOLATION
- D
IGITAL
Basic insulation, IEC 61010-1 (3
rd
): Pollution degree II, Material IIIa, Altitude < 5000m, Overvoltage Category II, applicable
for secondary circuits derived from the Mains
Input channel to Ground
±250 V Peak continuous working voltage
Input channel to channel None, all channels share one ground pin
Impedance across barrier
1000pF || 10MΩ || Gas Discharge Tube rated for 600V
C
ONNECTOR
9 pin standard D-Sub Female socket
LXI S
PECIFICATIONS
N
ETWORK
C
ONNECTION
10/100 Base-T (auto MDI-X)
LXI C
LASS
C
OMPLIANCE
(
V
1.4)
LXI Core + Clock Synchroni Event Mes Event Logs + Time Stamped
Data + IPv6 Support
C
LOCK
S
PECIFICATIONS
Clock oscillator accuracy
Synchronization accuracy
Default 1588 Sync threshold
Timestamp
Accuracy
Resolution
±20 ppm (when free running as Master, with no other clocks)
±20 ns typical (with high-quality IEEE 1588 grandmaster and transparent clocks).
Reports “synchronized” when < ±300 ns of the 1588 master clock
Configurable (default is 300 ns)
As good as time synchronization down to 40 ns
40 ns
IEEE 1588-
BASED
T
RIGGER
T
IMING
Alarm
Trigger time accuracy
Time to trigger delay
Receive LAN[0-7] Event
Trigger time accuracy
Time to trigger delay
Future timestamp
Past/zero timestamp
As good as time synchronization down to 40 ns
40 ns
As good as time synchronization down to 40 ns
40 ns typical
Unspecified (Based on processor workload)
H
ARDWARE
T
RIGGER
T
IMING
DIO IN time to trigger delay Min: 50 ns, Max: 100 ns
EXT TRIG in to timestamp delay Min: 46 ns, Max: 86 ns
Internal event/state to EXT TRIG
OUT time delay Min: 40ns, Max: 80ns
Internal event/state to DIO OUT
time delay Min: 50 ns, Max: 100 ns
LAN event in with event time !=0 0 to 40ns (because of clock granularity)
LAN event in with event time == 0 (unspecified)
LAN event out timestamp
granularity 40ns
I
NTERNAL
D
ATA
S
TORAGE
64 MSamples, shared among all enabled channels
(~6.6 minutes when sampling all 16 inputs at 10kSPS)