Vig410P Motherboard Manual
13
Chipset Overview
Built upon the functionality and the capability of the Intel 5500 chipset platform, the
Vig410P Motherboard provides the performance required for dual processor- based
CAD workstations or graphic-intensive systems. The 5500 chipset consists of the 5500
(LGA 1366) processor, the 5500 (North Bridge), and the South Bridge (ICH10R). With
the Intel QuickPath interconnect (QPI) controller built in, the 5500 Series Processor
platform is the first dual-processing platform that offers the next generation point-to-
point system interconnect interface, replacing the current Front Side Bus Technology
that substantially enhances system performance with increased bandwidth and
scalability.
The 5500 North Bridge connects to each processor through an independent QPI link.
Each link consists of 20 pairs of unidirectional differential lanes for transmission and
receiving in addition to a differential forwarded clock. A full-width QPI link pair provides
84 signals. Each processor supports two QPI links, one going to the other processor
and the other to the North Bridge.
The 5500 Chipset supports up to 24 PCI Express Gen2 lanes, peer-to-peer read and
writes transactions. The ICH10R provides up to six PCI-Express ports, six SATA ports
and eight USB connections.
In addition, the 5500 platform also supports a wide range of RAS (Reliability,
Availability and Serviceability) features. These features include memory interface ECC,
x4/x8 Single Device Data Correction (SDDC), Cyclic Redundancy Check (CRC), parity
protection, out-of-band register access via SMBus, memory mirroring, memory sparing,
and Hot-plug support on the PCI-Express Interface.
Main Features of the 5500 Series Processor and 5500
Chipset
Four processor cores in each processor with 8MB shared cache among cores
Two full-width Intel QuickPath interconnect links, up to 6.4 GT/s of data transfer rate
in each direction
Virtualization Technology, Integrated Management Engine supported
Point-to-point cache coherent interconnect, Fast/narrow unidirectional links, and
Concurrent bi-directional traffic
Error detection via CRC and Error correction via Link level retry
