Carrier Board Design Guide for SOM-9X35 Module
35
4.2.2
MIPI DSI Layout & Routing Recommendations
DSI Signal
Differen�al Pair
S1
S
S
Reference Plane
W
W
Sig M
Sig P
Figure 44: MIPI DSI differential trace width and spacing example
Metrics
Information/Design Guidance
General Information
Data rate
DSI – 2.1Gbit/s per lane
Impedance
Differential
Main route
100Ω ± 3%
Connector
100Ω ± 10%
Single-ended
Main route
50Ω ± 20%
Connector
50Ω ± 30%
Length match
(including SOM-9X35)
Differential pair trace mismatch
<5mil
Pair to pair trace mismatch
<27mil
Data-to-clock slew
<55mil
Maximum trace length
6000 mil
Spacing
Spacing to all other signals
4 x line width
Spacing data lane-to-lane
3 x line width
Table 11: MIPI DSI layout guidelines
The carrier board MIPI DSI trace length and mismatch calculations should take into account the MIPI DSI Bus
from the SOM-9X35 module.
Net Name
Trace
Length
(mil)
Length
Spec (mil)
Length
Mismatch
(mil)
Length
Mismatch
Spec (mil)
Total
Delay
(Trace +
Via) (ps)
Delay
Mismatch
(ps)
Delay
Mismatch
Spec (ps)
Notes
DSI_D2P
1504.27
6000
-0.55
6.75
252.61
0.14
1
Inter-pair
DSI_D2N
1504.82
252.47
DSI_D2P
-9.52
23.8
0.35
5
Pair-to-Pair
DSI_D2N
-10.53
-0.07
DSI_D0P
1536.50
6000
4.44
6.75
253.71
0.20
1
Inter-pair
DSI_D0N
1532.06
DSI_D0P
22.70
23.8
1.45
5
Pair-to-Pair
DSI_D0N
16.71
0.97
DSI_CKP
1513.79
6000
-1.55
6.75
252.26
-0.28
1
Inter-pair
DSI_CKN
1515.35
252.54
DSI_D1P
1530.18
6000
-2.59
6.75
253.24
-0.23
1
Inter-pair
DSI_D1N
1532.77
253.47
DSI_D1P
16.38
23.8
0.97
5
Pair-to-Pair
DSI_D1N
17.42
0.92