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Carrier Board Design Guide for SOM-9X35 Module

19

PIN#

PIN Name

GPIO#

Voltage 

Level

Power

Domain

I/O

Reset

Assignment

Function

J2.6

ACCDET

MT6390/

MT6357 

ACCDET

2.8V

AVDD28_

MIC

AI

ACCDET

Earphone MIC, 

ACCDET

J2.7

USB_DM_P0 MT8365 

USB_DM_P0

3.3V

AVDD33_

USB

AIO

USB_DM_P0 1st USB2.0 OTG D-

J2.8

AU_VIN0_N

MT6390/

MT6357 

AU_VIN0_N

2.8V

AVDD28_

MIC

AI

AU_VIN0_N

On board MIC, 

Differential MIC0- 

input,

J2.9

USB_DP_P0 MT8365 

USB_DP_P0

3.3V

AVDD33_

USB

AIO

USB_DP_P0 1st USB2.0 OTG D+

J2.10 AU_VIN0_P

MT6390/

MT6357 

AU_VIN0_P

2.8V

AVDD28_

MIC

AI

AU_VIN0_P

On board MIC, 

differential MIC0+ 

input, need Vbias on 

carrier board

J2.11

GND_SIGNAL Ground

Power

Ground

SIGNAL Ground

J2.12 AVSS28_AUD

MT6390/

MT6357 

AVSS28_AUD

AIO

AVSS28_AUD

Audio analog ground, 

add a 0 Ohm resistor 

to ground (Carrier 

board)

J2.13

USBOTG_

VBUS

USBOTG_

VBUS

5V

USBOTG_

VBUS

Power

USBOTG_

VBUS

1st USB2.0 OTG VBUS 

power for detect

J2.14

AU_HPR

MT6390/

MT6357 

AU_HPR

2.8V

AVDD28_

AUD

AO

AU_HPR

Headphone audio 

right channel output

J2.15

USBOTG_ID

MT8365 

EINT23/

GPIO23/

KPROW1/

I0:IDDIG/

O:WIFI_TXD/

O*CLKM3

1.8V

DVDD18_

IO1

I, PD

IDDIG

1st USB2.0 OTG ID 

input, High: device, 

Low: Host

J2.16

AU_HPL

MT6390 

AU_HPL

AO

AU_HPL

Headphone audio left 

channel output

J2.17

USBOTG_

DRVVBUS

MT8365 

EINT25/

GPIO25/

B1:KPCOL1/

O:USB_

DRVVBUS

1.8V

VDD18_IO1 I, PD

USBOTG_

DRVVBUS

1st USB2.0 OTG 

DRVVBUS output, 

High active

J2.18

GND_SIGNAL Ground

Power

Ground

SIGNAL Ground

J2.19

GND_SIGNAL Ground

Power

Ground

SIGNAL Ground

J2.20

EXT_GPIO3

MT8365 

EINT130/

GPIO130/

O*TDM_

TX_LRCK/

O*I2S3_LRCK

1.8V

DVDD18_

IO1

I, PD

EXT_GPIO3

MT8365  GPIO130, 

default for SPI_BUSY, 

input, high active

J2.21

CS_N

MT6390/

MT6357 

CS_N

0~4.2V

Vbattery

AI

CS_N

Battery Gas Gauge 

CS_N

Summary of Contents for SOM-9X35

Page 1: ...DESIGN GUIDE Carrier Board for SOM 9X35 Module 1 00 18012022...

Page 2: ...ies implied or otherwise in regard to this document and to the products described in this document The information provided in this document is believed to be accurate and reliable as of the publicati...

Page 3: ...Carrier Board Design Guide for SOM 9X35 Module iii Revision History Revision Date Description 1 00 18 01 2022 Initial release...

Page 4: ...hing 11 3 SOM 9X35 Module M 2 Slot Specification Overview 15 3 1 SOM 9X35 Module Placement 15 3 2 SOM 9X35 Module Carrier Board Dimensions 16 3 3 M 2 Slot 17 3 3 1 M 2 Slot Dimensions 17 3 3 2 M 2 Slo...

Page 5: ...4 9 ADC Interface 59 4 9 1 ADC Signal Definition 59 4 9 2 ADC Design Notes 59 4 10 System Boot Interface 60 4 10 1 System Boot Signal Definition 60 4 10 2 System Boot Design Notes 60 4 10 3 System Bo...

Page 6: ...Carrier Board Design Guide for SOM 9X35 Module vi 4 17 1 Gas Gauge Signal Definition 69 4 17 2 Gas Gauge Design Notes 70...

Page 7: ...rable on same layer 13 Figure 26 Preferred symmetrical breakout 13 Figure 27 Preferred breakout of differential pairs 14 Figure 28 SOM 9X35 module placement example on the carrier board 15 Figure 29 D...

Page 8: ...rcuitry 58 Figure 72 GPIO expander reference circuitry 59 Figure 73 ADC reference circuitry 60 Figure 74 SOM 9X35 power switch reference circuitry 61 Figure 75 SOM 9X35 BATSNS reference circuitry 61 F...

Page 9: ...e via delay 44 Table 21 SOM 9X35 MIPI CSI0B 2 lane trace via delay 44 Table 22 SOM 9X35 MIPI CSI1 4 lane trace via delay 45 Table 23 USB signal definition 48 Table 24 USB layout guidelines 49 Table 25...

Page 10: ...is not intended to be a specification All information and examples listed below are considered to be accurate as of the publication date However developers must be aware that this document is only a r...

Page 11: ...gh Definition Multimedia Interface I O Input Output I2C Inter IC IC Integrated Circuit LCD Liquid Crystal Display LVDS Low Voltage Differential Signaling M 2 Next Generation Form Factor MIPI Mobile In...

Page 12: ...ogrammable options following the colon PD nppukp default pull low pull down with programmable options following the colon PU nppdkp default pull high pull up with programmable options following the co...

Page 13: ...by reference layers The following figures show examples of microstrip and stripline designs Microstrip Stack Up Design Signal layers Reference layers Component layer Ground layer Inner layer Power lay...

Page 14: ...YER 5 LAYER 6 GROUND2 1 0oz 1 2mil Copper foil BOTTOM 0 5 oz 0 8mil Solder mask 0 4mil Er 3 5 Pla ng 0 8mil Copper foil Plating INNER2 1 0oz 1 2mil Copper foil Figure 04 6 Layer PCB board stack up det...

Page 15: ...ubs which can result in ringing on the rising edge caused by the high impedance of the output buffer in the high state In order to maintain better signal quality transmission stubs should be kept as s...

Page 16: ...ltage Signal 20 or wider 20 or wider Power 30 or wider 20 or wider Table 04 Recommended trace width and spacing General rules for minimizing crosstalk in high speed bus designs are listed below Maximi...

Page 17: ...reference ground planes That is a clock trace should be right beneath or on top of its reference ground plane see Figure 11 The series terminations damping resistors are needed for all clock signals t...

Page 18: ...the bends should be at least 1 5 times the trace width 4x trace width 1 5x trace width 1 5x trace width Figure 14 Suggested minimum distance and segment length at bends 2 2 5 Signal Proximity A minim...

Page 19: ...and reference plane A wide trace has lower impedance than a thin one with the same distance The same effect also exists for connector and component pads A large pad has significantly lower impedance...

Page 20: ...n the same layer place same amount of vias 2 2 9 Length Matching High speed interfaces have additional requirements regarding the time of arrival skew between different traces and pairs of signals For...

Page 21: ...gth Matching Except Package Breakout The following figure shows the requirements for length matching except package breakout The serpentine traces should be placed at the origin of the length mismatch...

Page 22: ...RC may only check the length difference over the whole connection Figure 24 Length differences need to be compensated in each segment The signal speed is not equal for different layers Since the diffe...

Page 23: ...14 If the space between the pads permits try to add a small loop to the shorter trace This is the preferred solution for matching the length difference as opposed to creating a serpentine trace Figur...

Page 24: ...erview 3 1 SOM 9X35 Module Placement The following figure shows the depiction of the top view of the carrier board PCB with the appropriate amount of space reserved for the SOM 9X35 module 45mm 60mm S...

Page 25: ...ons The following figures show the mechanical dimensions of the SOM 9X35 module and the reference carrier board VAB 935 Figure 29 Dimensions of the SOM 9X35 module 3 1mm 95 2mm 102mm 3mm 3mm 67 5mm 13...

Page 26: ...odule Table 5 shows the specifications of the sample M 2 slot M 2 Slot VIA Part Number Description 99H30 071127 Conn Slot 2E0BC21 S85BM 7H M 2 NGFF Connector KEYM 75PIN SMD right angle black LCP H 8 5...

Page 27: ...J1 J2 77 75 151 74 75 2 2 Figure 33 M 2 slot placement 3 4 M 2 Slot Pin Assignments The M 2 slot consists of 132 pins The pinouts of the M 2 slot are shown below PIN PIN Name GPIO Voltage Level Power...

Page 28: ...a 0 Ohm resistor to ground Carrier board J2 13 USBOTG_ VBUS USBOTG_ VBUS 5V USBOTG_ VBUS Power USBOTG_ VBUS 1st USB2 0 OTG VBUS power for detect J2 14 AU_HPR MT6390 MT6357 AU_HPR 2 8V AVDD28_ AUD AO A...

Page 29: ...SPI_CS MT8365 EINT26 GPIO26 O SPI_CSB 1 8V DVDD18_ IO3 I PD SPI_CS SPI_CS SPI Bus chip select output default for motor driver J2 27 SDA0 MT8365 EINT57 GPIO57 B1 SDA0_0 1 8V DVDD18_ IO1 I PU SDA0 I2C0...

Page 30: ...rupt input High active J2 34 GND_SIGNAL Ground Power Ground SIGNAL Ground J2 35 EXT_INT1 EINT67 GPIO67 I0 CMPCLK O TDM_ RX_BCK B0 I2S0_BCK 1 8V DVDD18_ IO3 I PD EXT_INT1 MT8365 EINT67 Reserved J2 36 U...

Page 31: ...3V HDMI_ VCC33 AO TX_CH1_P HDMI1 4 output TX_ D1 J2 44 MCU_INT MT8365 EINT132 GPIO132 O TDM_ TX_DATA0 O I2S3_DO 1 8V DVDD18_ IO1 I PD EINT132 MCU_INT interrupt input high active connect to MCU J2 45 T...

Page 32: ...ve suspend on J2 57 TX_CLK_M LT8618SXB TX_CLK 3 3V HDMI_ VCC33 AO TX_CLK_M HDMI1 4 output TX_CLK J2 58 PWM_A MT8365 EINT114 GPIO114 I0 I2S0_DI O I2S1_DO I0 I2S2_DI O I2S3_DO O PWM_A I0 SPDIF_IN 1 8V D...

Page 33: ...ront camera and MCU IO extender J1 8 MSDC1_INSI MT8365 EINT63 GPIO63 B1 SDA3_0 1 8V DVDD18_ IO3 I PU GPIO63 SD Card detect input Low active J1 9 SCL2 MT8365 EINT62 GPIO62 B1 SCL2_0 1 8V DVDD18_ IO3 I...

Page 34: ...OUT 3 0V DVDD28_ MSDC1 I PU MSDC1_DAT2 SDIO3 0 Bus DAT2 connect to SD Card J1 23 CSI1A_L2N MT8365 CSI1A_L2N 1 2V AVDD12_ CSI0 AI CSI1A_L2N Camera2 MIPI CSI1 4 lane CLK J1 24 SCL1 MT8365 EINT60 GPIO60...

Page 35: ...S_ TX_CKP 1 8V AVDD18_ DSI AO DSI_D1P LCM MIPI DSI 4 lane D1 LVDS TX 4 lane CK J1 39 CSI0B_L2N MT8365 CSI0_ RDN1_B 1 2V AVDD12_ CSI0 AI CSI0B_L2N Camera1 MIPI CSI0 B 2 lane D1 J1 40 DSI_D1N MT8365 DSI...

Page 36: ...0 4 lane D2 CSI0A 2 lane D0 J1 56 DSI_D0P MT8365 DSI_ D0P LVDS_ TX_D1P 1 8V AVDD18_ DSI AO DSI_D0P LCM MIPI DSI 4 lane D0 LVDS TX 4 lane D1 J1 57 CSI0A_L0P MT8365 CSI0_RDP2 CSI0_RDP0_A 1 2V AVDD12_ CS...

Page 37: ...1 M 2 Slot Reference Schematics CHASIS6_GND C1 0 1uF 50V X7R C3 0 01uF 50V NUT3 071CAAAZ90B 1 R1 1M X7R CHASIS7_GND C2 0 1uF 50V X7R C4 0 01uF 50V NUT2 071CAAAZ90B 1 R2 1M X7R VSYS VSYS_SUS C20 4700pF...

Page 38: ...ST LCM_ENP DISP_PWM DSI_D0_P DSI_D0_N DSI_D2_P DSI_D2_N DSI_CK_P DSI_CK_N DSI_D1_P DSI_D1_N DSI_D3_P DSI_D3_N 12 11 11 12 12 13 13 13 13 13 13 13 13 13 13 14 14 14 23 7 14 23 7 7 7 7 7 7 21 7 Figure 3...

Page 39: ...X _CH0_M J2 51 AO HDMI differential transmit 0 minus TX _CH0_P J2 49 AO HDMI differential transmit 0 plus TX _CH1_M J2 45 AO HDMI differential transmit 1 minus TX _CH1_P J2 43 AO HDMI differential tra...

Page 40: ...nded Main route 50 20 Connector 50 30 Length match Differential pair trace mismatch 5mil Pair to pair trace mismatch 27mil Spacing Spacing to all other signals 4 x line width Spacing data lane to lane...

Page 41: ...15 16 17 18 19 G1 G2 G4 G3 HDMI_OUT_D2 HDMI_OUT_D1 HDMI_OUT_D0 HDMI_OUT_D3 HDMI_OUT_D2 HDMI_OUT_D1 HDMI_OUT_D0 HDMI_OUT_D3 SDA_OUT SCL_OUT 5V_HDMI_OUT HDMI_OUT_HPD HDMI_OUT_CEC TX_CH1_M TX_CH1_P TX_CH...

Page 42: ...6 7 9 10 HDMI_OUT_D3 HDMI_OUT_D0 HDMI_OUT_D0 HDMI_OUT_D3 Figure 41 HDMI reference circuitry Part 2 For the HDMI compliance test 5V_HDMI should be less than 5 3V 0mA and more than 4 8V 55mA It is high...

Page 43: ...positive DSI_CKN J1 46 AO MIPI display serial interface clock negative DSI_D2N J1 50 AO MIPI display serial interface lane 2 negative DSI_D2P J1 52 AO MIPI display serial interface lane 2 positive DS...

Page 44: ...a lane to lane 3 x line width Table 11 MIPI DSI layout guidelines The carrier board MIPI DSI trace length and mismatch calculations should take into account the MIPI DSI Bus from the SOM 9X35 module N...

Page 45: ...m LCP BLACK 3 4 5 6 7 2 9 10 11 12 13 14 15 16 17 18 19 20 21 22 8 1 G1 G2 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 DSI2_DN1 1 DSI2_ID1 1 DSI2_LEDK1 1 C160 0 1uF 16V X7R DSI2_DP1 1 C170 0 1u...

Page 46: ...uF 50V X7R CAP0805 LCD_VBIAS_VGH1 LCD_VBIAS_VGL LCD_VBIAS_SW LCD_VBIAS_SW2 LCD_VBIAS_SW1 LCD_VBIAS_FB LCD_VBIAS_EN LCD_VBIAS_SW3 LCD_VBIAS_VGH2 330_1 VGL C200 0 022uF 16V X7R 4V6_VDD to LCD_VIN Switch...

Page 47: ...High active LCM_ENP J1 70 GPIO116 1 8V I PD LCM power enable output High active LCM_ENN J1 68 GPIO127 1 8V I PD LCM AVDD enable Output High active Table 13 LVDS signal definition Route Di eren ally Ro...

Page 48: ...ce Via ps Delay Mismatch ps Delay Mismatch Spec ps Notes LVDS_TX_D0P 1504 27 4000 0 55 6 75 252 61 0 14 1 Inter pair LVDS_TX_D0N 1504 82 252 47 LVDS_TX_D0P 25 91 29 74 0 63 5 Pair to Pair LVDS_TX_D0N...

Page 49: ...6V X6S C265 0 1uF 16V X7R FB17 BLM15PX121SN1D 120 OHM 2000mA VDDIO_LCD C253 0 1uF 16V X7R R159 10K LVDS_LCD_PWM VDDIO_LCD R165 10K R164 10K X LCD_SELB LCM_LEDA LCD_VGH LCM_LEDK LCD_AVDD LCD_VCOM LVDS_...

Page 50: ...itive CSI0_RCP_B CSI0_RDP3 CSI0A_L0N J1 55 AI MIPI CSI0A serial interface lane 0 negative CSI0_RDN0_A CSI0_RDN2 CSI0A_L0P J1 57 AI MIPI CSI0A serial interface lane 0 positive CSI0_RDP0_A CSI0_RDP2 CSI...

Page 51: ...signal definition Route Di eren ally Route Di eren ally Route Di eren ally Route Di eren ally Route Di eren ally Route Di eren ally Route Di eren ally Route Di eren ally Route Di eren ally Route Di e...

Page 52: ...5 module Net Name Trace Length mil Length Spec mil Length Mismatch mil Length Mismatch Spec mil Total Delay Trace Via ps Delay Mismatch ps Delay Mismatch Spec ps Notes CSI0A_L0P 1905 844 6000 1 39 6 7...

Page 53: ...35 module MIPI CSI0B 2 lane bus from the SOM 9X35 module Net Name Trace Length mil Length Spec mil Length Mismatch mil Length Mismatch Spec mil Total Delay Trace Via ps Delay Mismatch ps Delay Mismatc...

Page 54: ...MIPI CSI1 4 lane trace via delay 4 4 3 MIPI CSI Reference Schematics The carrier board must use a 24MHz Oscillator to generate the main clock to the camera module The oscillator s power should be sup...

Page 55: ...down pins It is recommended to use an I O on the expander to control the cameras as there are only 6 GPIOs assigned on the SOM 9X35 module s golden finger Ensure that the I O on the expander is the sa...

Page 56: ...CAM1_GND3 1 CAM1_GND1 1 CAM1_RDN1 1 CAM1_CKP1 1 CAM1_RDP1 1 CAM1_GND2 1 CAM1_CKN1 1 CAM1_RDN3 1 CAM1_DVDD1 1 J15 51536 02641 AS1 26PIN 0 5mm RIGHT ANGLE BOTTOM CONTACT 3 4 5 6 7 2 9 10 11 12 13 14 15...

Page 57: ...ne camera reference circuitry Part 2 4 5 USB Interface The SOM 9X35 module features two USB interfaces USB 2 0 Host and USB 2 0 OTG The USB Port1 interface can only be used as a host while the USB Por...

Page 58: ...9X35 Differential pair trace mismatch 5mil Maximum trace length 10000 mil Spacing Spacing to all other signals 4 x line width Spacing data lane to lane 3 x line width Table 24 USB layout guidelines If...

Page 59: ...ce via delay 4 5 3 USB Reference Schematics 0 5A 0 5A limit 6 8 Rset Kohm 6 8 12 567mA Rset Rds on 0 1Ohm R2 2021 3 23 for EMI Debug issue C112 0 1uF 0 022uF 5V_SUS 5V_SUS 5V_OTG USBOTG_DRVVBUS 5 C108...

Page 60: ...UT1_HUB 12MHz_OUT_HUB 12MHz_IN_HUB 3V3_SUS D3V3_HUB 3V3_VCC C97 0 22uF 16V X7R C96 0 1uF 16V X7R C95 0 01uF 16V X7R R689 0 X FB9 BLM15PX121SN1D 120 OHM 2000mA C99 10uF 10V X7R C98 0 01uF 16V X7R A m 0...

Page 61: ...SDC signal definition SOM 9X35 M 2 Slot Edge nger SDC2_DATA_0 SDC2_DATA_1 SDC2_DATA_2 SDC2_CMD SD_CARD_DET_N SD_WP SDC2_DATA_3 ESD Protec on SD 3 0 SDC2_CLK Figure 63 SDC routing topology 4 6 2 SDC L...

Page 62: ...ane to lane 2 x line width Table 30 SDC layout guidelines The carrier board SDC trace length and mismatch calculations should take into account consider the SDIO bus from the SOM 9X35 module Net Name...

Page 63: ...VDD 4 CLK 5 VSS 6 DAT0 7 DAT1 8 GND G1 GND G2 GND G3 GND G4 GND G5 FB71 BLM15PX121SN1D C762 39pF 50V NPO C760 2700pF 50V X7R C761 270pF 50V X7R SD_DAT4 1 SD_VCC1 1 C76 2 2uF 10V X7R SD_DET1 1 C77 0 1...

Page 64: ...0 3ohm and a rated current 30mA is recommended An independent 3 0V LDO is required to supply MIC Vbias 3V0 Vref 0 8V 3V3_VCC 3V0_VCC R326 43K_1 U32 ETA5050V0S2F VIN 1 GND 2 EN 3 FB 4 VOUT 5 R322 120K...

Page 65: ...10K ESD52 TLSD05CBL 5V 5pF 1 2 C551 22uF 10V X7T CAP0805 ESD51 TLSD05CBL 5V 5pF 1 2 J19 PJD 035 67S1A01 3 4 2 5 1 G1 FB44 BLM15AG221SN1D 220 OHM 300mA C549 100pF R323 47K_1 C556 390pF C554 33pF 50V NP...

Page 66: ...70K X MUTE_PA Class D Amp VDD_AMP1 VDD_AMP1 4V6_VDD AU_HP_LEFT 5 22 AU_HP_RIGHT 5 22 C578 0 01uF 16V X7R C583 22uF 10V X7T CAP0805 R343 10K X C582 0 1uF 16V X7R C576 0 1uF X 16V X7R C577 0 1uF 16V X7R...

Page 67: ...terrupt input High active EXT_INT1 J2 35 GPIO67 1 8V I PD MT8365 EINT67 Reserved EXT_GPIO3 J2 20 GPIO130 1 8V I PD MT8365 GPIO130 default for SPI_BUSY input High active EXT_GPIO2 J2 22 GPIO131 1 8V I...

Page 68: ...P2 nINT_IOEXP2 1V8_VCC C758 0 1uF 16V X7R FB70 BLM15PX121SN1D 120 OHM 2000mA C618 2 2uF 10V X7R 1V8_IO_EXP2 RPI_GPIO10 CAM1_PDN CAM1_RESET CAM2_PDN CAM2_RESET CAM3_PDN CAM_EN_POWER 4G_W_DISABLE 4G_PER...

Page 69: ...he VSYS PIN J2 71 J2 72 J2 75 If the J2 25 V BATSNS 3 0V or V BATSNS 4 25V is used the PMU MT6390 MT6357 will judge the whether the lithium ion battery is faulty and the system will not boot If the J1...

Page 70: ...45 1000pF 50V X7R C355 1000pF X 50V X7R J17 2417SJ 07 F3 1 2 3 4 5 6 7 R241 0 X VPACK 1 1 R250 0 R693 100K_1 VPACK NTC_BAT NTC1_BAT NTC_CHG VBAT1 VBAT1 BATSNS 5 25 R236 1M_1 Opera onal Ampli er 2 7 24...

Page 71: ...al Name Pin I O Pad Characteristics Description Voltage Type SDA2 J1 7 GPIO61 1 8V I PU I2C2 SDA default connect to front Camera and MCU IO extender SCL2 J1 9 GPIO62 1 8V I PU I2C2 SCL default connect...

Page 72: ...I2C level shift IC reference circuitry If an I2C Device Host power is not present simultaneously when the system is suspended or powered off a level shift is required Note The N Channel MOS FET should...

Page 73: ...r SPI Bus together and do not trace with other critical signals MIPI or RF trace If the UART or SPI Buses device power domain is 2 5V or 3 3V a level shift is required ex motor driver To avoid power l...

Page 74: ...ETR ADC1_IN1 COMP1_INP 5 VSS1 VSSA VREF 6 VDD1 VDDA VREF 7 PD0 TIM3_CH2 ADC1_TRIG ADC1_IN22 COMP2_INP COMP1_INP 8 PD1 TIM1_CH3 TIM3_ETR ADC1_IN21 COMP2_INP COMP1_INP 9 PD2 TIM1_CH1 ADC1_IN20 COMP1_INP...

Page 75: ...13PSAC TRG 20V 3 5A G D S R619 100K_1 C323 1uF 50V X7R BAT1 50273 0027N 001 1 2 G1 G2 RTC_1V8 1 C741 0 01uF X 16V X7R VIN_1V8_RTC EN_1V8_RTC VIN_1V8_RTC EN_1V8_RTC FB_1V8_RTC BP_1V8_RTC FB_1V8_RTC Fig...

Page 76: ...Power supply detect MCU enter low power mode when detect Low High power supply Low Power remove 25 PC4 I ADC BATTERY VOLTAGE ADC INPUT 26 PC5 I OSC32_IN OSC32_IN 27 PC6 O OSC32_OUT OSC32_OUT 8 PD0 O...

Page 77: ...ESET Figure 83 SOM 9X35 reset button reference circuitry Do not pull the KPCOL0 J2 52 pin High on the carrier board as it is already pulled High to 1 8V on SOM 9X35 module Download Bu on KPCOL0 5 15 C...

Page 78: ...status Pin Name Power off System Work System Suspend J2 54 EXT_3V3_ENABLE Low High Low J2 56 EXT_PMIC_EN1 Low High High Table 43 SOM 9X35 power management status The EXT_PMIC_EN1 J2 56 pin is used to...

Page 79: ...power leakage VPACK VBAT1 EN_MAIN_PWR 5 16 19 Q58 SM2313PSAC TRG 20V 3 5A G D S R629 1M_1 Q59 LMBT3904TT1G 1 2 3 R631 0 X R628 470K Figure 86 SOM 9X35 battery leakage protect reference circuitry 2 Ce...

Page 80: ...divided circuit voltage following circuit is required VBAT1 VBAT1 BATSNS 5 25 R236 1M_1 Opera onal Ampli er 2 7 24Vcc 2 8uA Iq Bandwidth 100KHz U54 SGM8240 1AXN5G TR 3 4 1 5 2 C344 0 1uF 16V X7R R630...

Page 81: ...0 687 4654 Email embedded viatech com Email embedded via tech eu Taiwan Headquarters USA Europe Tsinghua Science Park Bldg 7 No 1 Zongguancun East Road Haidian Dist Beijing 100084 China Tel 86 10 5985...

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