5-4
VL-12CT96/7 Analog & Digital I/O Card
Signal Inversion
All parallel port circuits on the VL-12CT96/7 board are inverting. A high logic level on connector J3
is represented by a 0 in the PARLO or PARHI register, and a low logic level is represented by a 1.
Since Opto 22 modules invert the logic sense of signals passed through them, the register-to-module
interface is effectively positive logic. The resulting data interface levels between the VL-12CT96/7 and
I/O rack modules are shown in Figure 5-1.
Data
I/O
Output
Input
I/O
Data
Written
Pin
Modules
Modules
Pin
Read
0
(1)
Power off
Voltage absent
(1)
0
1
(0)
Power on
Voltage present
(0)
1
Figure 5-1. I/O Module Data Interface
Digital Input
The logic state of the parallel input channels can be read at any time by reading the PARLO or PARHI
registers. Simply choose the correct register and read it as an 8-bit quantity. If desired, both registers
can be read with a single 16-bit input transaction (in ax,dx) by addressing PARLO. This works with
both 8 and 16-bit data modes. If using STD 32, this data transfer will take a single bus cycle. See page
4-12 for further information on register access.
Interrupt Mode Digital Input
One of four parallel port signals can be selected by jumper V13 to trigger an interrupt request when
the logic state on these signals changes state.
Two edge options are available: single edge, and double edge mode. Single edge mode generates an
interrupt when the selected input signal (at connector J3) switches from high-to-low. Double edge
mode generates an interrupt on both high-to-low and low-to-high transitions.
The interrupt request signal is cleared when either the PARLO or PARHI register is read.
Digital Output
The logic state of any parallel output channel can be manipulated at any time by writing to the PARLO
or PARHI registers. Simply choose the correct register and write the digital value to it as an 8-bit
quantity. If desired, both registers can be written to with a single 16-bit output transaction (out dx,ax)
by addressing PARLO. This works with both 8 and 16-bit data modes. If using STD 32, this data
transfer will take a single bus cycle. See page 4-12 for further information on register access.
System Reset
When the card is powered up, or a system reset occurs, the following happens:
• Analog input channel address is reset to zero.
• Analog input status flags are cleared.
• Analog outputs are reset to 0 volts.
• Digital outputs are reset to their inactive high states.
Operation — System Reset
Summary of Contents for VL-12CT96
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