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VersaLogic VL-12CT96, Reference Manual

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VersaLogic VL-12CT96 Reference Manual Download Page 28

3-2

VL-12CT96/7 Analog & Digital I/O Card

External Connections

J1, J2 and J3 are unlatched header type connectors.  External connections to the VL-12CT96/7 can be
made with standard cable assemblies, or with the following mating connectors:

Connector

Mating Connector

J1

26-pin socket type connectors such as 3M #3399-6626

J2

10-pin socket type connectors such as 3M #3473-6610

J3

34-pin socket type connectors such as 3M #3414-6634

Figure 3-1.  Mating Connectors

Figure 3-2.  I/O Connector Physical Pin Locations

Installation — External Connections

Summary of Contents for VL-12CT96

Page 1: ...Reference Reference Manual Manual VL 12CT96 VL 12CT97 VL 12CT98 Analog Digital Input Output Card for the STD 32 Bus ...

Page 2: ...ii VL 12CT96 7 Analog Digital I O Card ...

Page 3: ...op Mode 2 11 Input Range 2 12 Settling Time 2 13 Low Pass Filter 2 13 Input Resolution 2 14 Analog Output Configuration 2 15 Output Voltage Range 2 15 Output Local Remote Sense 2 15 Output Current Loop Option 2 16 Output Voltage Loopback 2 16 5B01 Analog Signal Conditioning Rack 2 17 Digital Input Output Configuration 2 17 Rack Power Control 2 17 Digital I O Interrupts 2 18 Edge Selection 2 18 Int...

Page 4: ...t Registers 4 12 Signal Direction 4 12 Parallel Port Data High Register 4 12 Parallel Port Data Low Register 4 12 5 Operation Analog Input 5 1 Polled Mode Analog Input 5 1 Interrupt Mode Analog Input 5 2 Analog Output 5 3 Digital I O 5 3 Signal Direction 5 3 Signal Inversion 5 4 Digital Input 5 4 Interrupt Mode Digital Input 5 4 Digital Output 5 4 System Reset 5 4 6 Software Examples Analog Input ...

Page 5: ...he analog sections these cards also include 16 digital I O lines These digital lines feature open collector outputs with readback and are compatible with optically isolated modular I O racks Features Analog Input Analog Input Analog Input Analog Input Analog Input 8 Differential or 16 Single Ended Input Channels 12 bit VL 12CT96 or 16 bit VL 12CT97 Resolution 5V and 10V Input Ranges 50 mv and 100 ...

Page 6: ...ime 35 volt input overvoltage protection 6 x 108 Ω input impedance 2 5 µA input bias current 12 volt common mode range 89 dB common mode rejection gain 1 Analog Output Analog Output Analog Output Analog Output Analog Output 2 channels 5V or 10V ranges 1 optional current loop output 15 µs settling time Resolution 12 bit Accuracy 0 024 5 ma maximum output current per channel Digital I O Digital I O ...

Page 7: ...orting plugs Features are selected or deselected by installing or removing the jumpers as noted The terms In or Jumpered are used to indicate an installed plug Out or Open are used to indicate a removed plug Figure 2 1 shows the jumper block locations on the VL 12CT96 7 card The figures indicate the position of the jumpers as shipped from the factory Configuration ...

Page 8: ...2 2 VL 12CT96 7 Analog Digital I O Card VL 12CT96 7 Jumper Block Locations Figure 2 1 Jumper Block Locations for VL 12CT96 7 Configuration Jumper Block Locations ...

Page 9: ...pendently V3 1 2 DAC Channel 0 Remote Sense IR Drop Compensation Local sense 2 15 In Local sense no compensation Out Remote sense V3 3 4 Channel 0 Output Range 5 Volt Selection 10V 2 15 In 5 Volts Out 10 Volts V3 5 6 Channel 0 Output Range 10 Volt Selection 10V 2 15 In 10 Volts Out 5 Volts V4 1 2 DAC Channel 1 Remote Sense IR Drop Compensation Local Sense 2 15 In Local sense no compensation Out Re...

Page 10: ...Pin 25 generates interrupt request Out Disabled V14 1 2 Use STD Bus IRQx to carry parallel port interrupt signal Disabled 2 19 In Connects parallel port interrupt circuitry to STD Bus IRQx E47 Out Frees IRQx to be used for other purposes V14 2 3 Use STD Bus IRQx to carry ADC conversion complete interrupt Disabled 2 19 In Connects ADC interrupt circuitry to STD Bus IRQx E47 Out Frees IRQx to be use...

Page 11: ...n page 4 1 for further information 8 Bit Addressing To configure the board for an 8 bit I O address refer to the figure below Use the table to select the jumpering for the appropriate upper hex digit of the desired starting address i e 3 and 0 hex address 30 Note the lower digit is always 0 V12 V12 V12 V12 Upper Lower 1 2 3 4 5 6 7 8 Digit Digit X X X X 0 Always 0 X X X 1 X X X 2 X X 3 X X X 4 X X...

Page 12: ... E X E X E F F F X Jumper installed Jumper removed Jumper Jumper Jumper Jumper Jumper As As As As As Block Block Block Block Block Description Description Description Description Description Shipped Shipped Shipped Shipped Shipped V9 Board Address A8 A15 0300H 1 2 In A15 Decoded Low 1 2 Out A15 Decoded High 3 4 In A14 Decoded Low 3 4 Out A14 Decoded High 5 6 In A13 Decoded Low 5 6 Out A13 Decoded ...

Page 13: ...Shipped Shipped Shipped Shipped Shipped V10 IOEXP Select IOEXP Ignored 1 2 In Board responds to IOEXP high and low IOEXP ignored 2 3 In Board responds to IOEXP low Both Out Board responds to IOEXP high Figure 2 5 IOEXP Options Data Bus Width The VL 12CT96 7 provides both 8 bit and 16 bit data paths to the bus The 8 bit mode is compatible with STD 80 STD Z80 and STD 32 bus specifications The 16 bit...

Page 14: ...ious equipment ground lines affect analog measurements made with reference to ground careful attention should be paid to the ground connections shown In particular the STD Bus power supply logic ground line should never be connected to earth ground when operating in the differential or pseudo differential modes Single Ended Mode Single ended mode is used for signals that are referenced to a common...

Page 15: ... of the advantages of full differential input while requiring fewer total wires 16 input channels are available in pseudo differential mode This mode is used when connecting to a 5B01 signal conditioning rack P D SENSE AGND CHANNEL 1 CHANNEL 0 OPTIONAL V1 V0 25 9 5 1 VL 12CT96 V1 1 7 11 9 3 5 5 6 2 8 10 12 4 6 9 7 10 8 VL 12CT97 1 3 V6 4 2 2 6 4 3 5 1 V7 Figure 2 7 Pseudo Differential Input Mode C...

Page 16: ...4 5 2 1 VL 12CT96 V1 11 9 5 3 7 1 12 10 6 4 8 7 9 8 10 VL 12CT97 2 3 1 5 2 4 6 V6 OPTIONAL 2 6 4 3 5 1 V7 SEE TEXT Figure 2 8 Differential Input Mode Note that in full differential operation a return path must be provided for the bias currents of the input amplifier An on board 1M Ω resistor is provided for this purpose Jumper V1 11 12 should be inserted In noisy electrical environments the bias r...

Page 17: ...e board must be jumpered for differential mode and the input range should be jumpered for 5V operation when using current loop inputs A signal proportional to the 4 20 ma current is developed across the precision resistors This voltage is applied to the VL 12CT96 7 as a differential mode signal and is converted into digital values CHANNEL 0 LOOP I 1 2 V1 11 9 7 3 5 1 10 12 3 1 5 8 4 6 9 7 2 4 6 V7...

Page 18: ...s operate with the same input range As shipped the board is configured for 10 volt operation It can be jumpered for other ranges as shown below Jumper Jumper Jumper Jumper Jumper As As As As As Block Block Block Block Block Description Description Description Description Description Shipped Shipped Shipped Shipped Shipped V1 3 4 Input Gain Normal In x100 Out Normal V6 1 8 InputRange 10V 1 2 7 8 In...

Page 19: ...g delay is needed for the 50 mv or 100 mv input ranges Settling delay times can be selected as indicated in the figure below Jumper Jumper Jumper Jumper Jumper As As As As As Block Block Block Block Block Description Description Description Description Description Shipped Shipped Shipped Shipped Shipped V7 3 4 5 µS Settling Delay Enabled In Enabled Out Disabled V7 5 6 10 µS Settling Delay Disabled...

Page 20: ...mper Jumper Jumper Jumper As As As As As Block Block Block Block Block Description Description Description Description Description Shipped Shipped Shipped Shipped Shipped V8 3 4 AnalogInputResolution Varies In 16 Bit Resolution VL 12CT97 only Out 12 Bit Resolution VL 12CT96 only Figure 2 15 Input Range Selection Analog Output Configuration The VL 12CT96 7 board accommodates two analog output chann...

Page 21: ... over a long cable the resistance of the wire can cause a voltage drop to occur This can result in erroneous signal levels at the remote end of the line The VL 12CT96 7 board can compensate for this drop up to 3 volts of loss by measuring the voltage at the far end of the line through a separate sense line Each channel can be jumpered for local sense voltage measured at the card edge no sense wire...

Page 22: ...97 VL 12CT96 Figure 2 18 Current Loop Connection OutputVoltage Loopback The output channels can be connected to their corresponding input channels for a direct readback of the voltage The looped back output channels are also available on J1 for user and 5B01 rack connections Jumper Jumper Jumper Jumper Jumper As As As As As Block Block Block Block Block Description Description Description Descript...

Page 23: ...en jumper V5 is installed the I O rack power line I O rack pin 49 is connected directly to 5 volts on the STD Bus If the I O rack is powered by a separate external supply either a jumper from the I O rack or the V5 jumper must be removed Note that the 5 volt power output from the VL 12CT96 7 card can be shorted to ground if the connector is not correctly oriented at either end of the interface cab...

Page 24: ...dule 2 Disabled In Activity on Module 2 J3 Pin 27 generates interrupt request Out Disabled V13 9 10 Parallel Port Interrupt Select Module 3 Disabled In Activity on Module 3 J3 Pin 25 generates interrupt request Out Disabled Figure 2 21 Digital Interrupts Edge Selection Two edge options are available single edge and double edge mode Single edge mode generates an interrupt when any of the selected i...

Page 25: ...d for other purposes V15 2 3 Use STD Bus IRQ to carry ADC conversion complete interrupt Enabled In Connects ADC interrupt circuitry to STD Bus IRQ P44 Out Frees IRQ to be used for other purposes V16 1 2 Use STD Bus IRQ1 to carry parallel port interrupt signal Enabled In Connects parallel port interrupt circuitry to STD Bus IRQ1 P37 Out Frees IRQ1 to be used for other purposes V16 2 3 Use STD Bus I...

Page 26: ...2 20 VL 12CT96 7 Analog Digital I O Card ...

Page 27: ... power on 20V with power off Each analog channel presents a minimum input impedance of 1 x 108 Ω Connector J2 is the analog output connector All signals are analog level signals The voltage outputs can provide up to 5 ma each The optional current loop output requires an external 15V to 30V power supply capable of providing 25 ma of current Connector J3 is the digital input output connector Each ci...

Page 28: ...th standard cable assemblies or with the following mating connectors Connector MatingConnector J1 26 pin socket type connectors such as 3M 3399 6626 J2 10 pin socket type connectors such as 3M 3473 6610 J3 34 pin socket type connectors such as 3M 3414 6634 Figure 3 1 Mating Connectors Figure 3 2 I O Connector Physical Pin Locations Installation External Connections ...

Page 29: ...round In pseudo differential configuration these inputs are considered high side inputs and are referenced to PD Channel 0 to 7 Differential high side voltages are applied to these inputs for A D conversion Each input is referenced to a corresponding differential low side input Channel 0 to 7 Differential low side voltages are applied to these inputs for A D conversion Each input is referenced to ...

Page 30: ...log voltage outputs referenced to analog ground Each signal can source or sink up to 5 mA DA0S DA1S Channel 0 1 Sense Remote sense inputs Used to compensate for the voltage drop which occurs when using long cables LP0 Channel 0 Loop Power External 15V to 30V power input Used to provide loop power for current loop mode DA0I Channel 0 Current Output Current loop output from channel 0 AGND Analog Gro...

Page 31: ... signals Each signal is an open collector driver with a 10ΚΩ pull up resistor to 5V Input gates are attached to each signal for read back The open collector driver must be in the off state to use a channel for input purposes Registers PARLO and PARHI are used to manipulate these signals Power 5V power output When jumper V5 is installed up to 500 mA can be drawn from this 5V output to power the Opt...

Page 32: ...3 6 VL 12CT96 7 Analog Digital I O Card ...

Page 33: ...litate efficient single cycle reading of the A D data 8 Bit Mode 8 Bit Mode 16 Bit Mode 16 Bit Mode As Shipped Input Port Output Port Input Port Output Port Port Address Address DAC1HI DAC1HI Board Address 15 030FH DAC1LO DAC1LO Board Address 14 030EH DAC0HI DAC0HI Board Address 13 030DH DAC0LO DAC0LO Board Address 12 030CH PARHI PARHI PARHI PARHI Board Address 11 030BH PARLO PARLO PARLO PARLO Boa...

Page 34: ...ort Figure 4 2 Read and Write Register Functions Analog Input Write Registers Control Register CONTROL 0300H 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Figure 4 3 Control Register The Control register is a write register used to configure the operating mode of the VL 12CT96 7 D7 Not Used This bit has no function on the VL 12CT96 7 D6 D5 Scan Range Limit These two bits define and restrict the number o...

Page 35: ...itial channel to be converted usually channel 0 should be selected by writing to the SELECT register D3 Auto Trigger Enable Setting this bit to 1 places the VL 12CT96 7 in auto trigger mode In this mode a new A D conversion is triggered immediately after the ADCHI register is read eliminating the need to trigger a conversion by writing to the CONVERT register There are two ways to trigger an A D c...

Page 36: ...the analog channel to use for A D conversion In auto increment mode the channel address changes after each A D conversion In all other cases the value remains static Note The Scan Range Limit bits in the Control register affect the number stored in this register See page 4 2 for further information A settling delay set by jumper V7 is inserted whenever this register changes D3 D2 D1 D0 SelectedCha...

Page 37: ...ELECT register out dx ax also writes into the CONVERT register causing channel addressing and triggering with one CPU instruction D7 D0 Not Used These bits have no function on the VL 12CT96 7 Any value written triggers an A D conversion Clear Flags Register CLRFLG 0309H 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Figure 4 8 Clear Flags Register The CLRFLG register is a write register which when writte...

Page 38: ...from the ADCLO and ADCHI registers When interrupts are enabled the A D interrupt request signal goes active when Done is set The Done bit is reset to 0 when the ADCHI register is read or it may be reset by writing to the CLRFLG register D5 Not Used This bit has no function on the VL 12CT96 7 D4 Settling Delay This bit is reset to 0 while the settling delay set by jumper V7 is in progress The bit i...

Page 39: ...hese bits contain data bits D7 through D0 of the conversion results See the A D Data Representation section on page 4 8 for a discussion of data format Analog Input Data High Register ADCHI 0304H 8 Bit mode 0305H 16 Bit mode 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Figure 4 11 A D Data High Register The ADCHI register is a read register containing the upper 8 bits of data from the A D conversion re...

Page 40: ...ata Step 0 00244140625 5V Range 0 0048828125 10V Range 0 0000244140625 50 mV Range 0 000048828125 100 mV Range Sample 12 bit two s complement values are shown in the table below 5V Input 10V Input 50mV Input 100mV Input Output Data Voltage Voltage Voltage Voltage Hex Dec Comment 5 0000 10 0000 0 0500 0 1000 Out of range 4 9976 9 9951 0 04998 0 09995 07FF 2047 Maximum positive voltage 2 5000 5 0000...

Page 41: ...V Range 0 000003051757813 100 mV Range Sample 16 bit two s complement values are shown in the table below 5V Input 10V Input 50mV Input 100mV Input Output Data Voltage Voltage Voltage Voltage Hex Dec Comment 5 000000 10 000000 0 050000 0 100000 Out of range 4 999847 9 999695 0 0499985 0 099996 7FFF 32767 Maximum positive voltage 2 500000 5 000000 0 025000 0 050000 4000 16384 Positive half scale 1 ...

Page 42: ...D0 of the 12 bit digital value to be converted to an analog output voltage See the D A Data Representation section on page 4 11 for a discussion of data format Analog Output Data High Register Channel 0 DAC0HI 030DH Channel 1 DAC1HI 030FH 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Figure 4 15 D A Data High Register The DAC0HI and DAC1HI registers are write registers which receive the upper 4 bits of ...

Page 43: ...gital A D Conversion Data Step 0 00244140625 5V Range 0 0048828125 10V Range 0 0000244140625 50 mV Range 0 000048828125 100 mV Range 5V Output 10V Output 4 20 ma Output Output Data Voltage Voltage Current Hex Dec Comment 4 9976 9 9951 20 0000 07FF 2047 Maximum positive voltage 2 5000 5 0000 12 0000 0400 1024 Positive half scale 1 2500 2 5000 8 0000 0200 512 Positive quarter scale 0 00244 0 00488 4...

Page 44: ...1 D0 Figure 4 17 Parallel Port Data High Register D7 D0 MOD0 MOD7 Data written to this register is driven onto the parallel port data signals MD0 MD7 on connector J3 This is an inverted data port when a bit is set to 1 the signal line is driven low when a bit is reset to 0 the signal line is driven high Data read from this register returns the current inverted input state of the parallel port sign...

Page 45: ...er information After the first channel selection this step can be skipped for multiple conversions of the same channel This will eliminate the settling delay which is inserted every time the SELECT register is written to A word wide output instruction to this register out dx ax also writes into the CONVERT register causing channel addressing and triggering with one CPU instruction Trigger A D conv...

Page 46: ...n ax dx will fetch data from both registers in the proper sequence Reading the ADCHI register clears the interrupt request The interrupt service routine can be written to select a different channel or trigger a new conversion Initialize VL 12CT96 7 for interrupt mode Set bit D0 in the CONTROL register See page 4 2 for further information Initialize VL 12CT96 7 for Auto trigger if desired Set bit D...

Page 47: ...d output registers Each channel has two registers DACxLO and DACxHI DACxLO should be written to first followed by DACxHI When DACxHI is updated the analog output value will change See page 4 10 for further information Determine address of desired channel Output data to channel register Low byte first high byte second or a single 16 bit output Digital I O Signal Direction All of the VL 12CT96 7 par...

Page 48: ...ccess Interrupt Mode Digital Input One of four parallel port signals can be selected by jumper V13 to trigger an interrupt request when the logic state on these signals changes state Two edge options are available single edge and double edge mode Single edge mode generates an interrupt when the selected input signal at connector J3 switches from high to low Double edge mode generates an interrupt ...

Page 49: ...lect equ 0301h Channel Select Register 0302 convert equ 0302h Convert Register 0303 adclo equ 0303h A D Data Low Register 0304 adchi equ 0304h A D Data High Register 0309 clrflg equ 0309h Clear Flags Register 030A parlo equ 030Ah Parallel Port Data Low Register 030B parhi equ 030Bh Parallel Port Data High Register 030C dac0lo equ 030Ch D A Channel 0 Data Low Register 030D dac0hi equ 030Dh D A Chan...

Page 50: ...a Low Register 0304 adchi equ 0304h A D Data High Register 0309 clrflg equ 0309h Clear Flags Register 030A parlo equ 030Ah Parallel Port Data Low Register 030B parhi equ 030Bh Parallel Port Data High Register 030C dac0lo equ 030Ch D A Channel 0 Data Low Register 030D dac0hi equ 030Dh D A Channel 0 Data High Register 030E dac1lo equ 030Eh D A Channel 1 Data Low Register 030F dac1hi equ 030Fh D A Ch...

Page 51: ...data segment register to 0036 8E D8 mov ds ax variable storage area 0038 C3 ret 0039 init_1296 init_1296 init_1296 init_1296 init_1296 VL 12CT96 7 INTERRUPT INITIALIZATION 0039 B0 01 mov al 01h CONTROL REGISTER 003B BA 0300 mov dx control D7 0 Scan Range Limit No limit 003E EE out dx al D6 0 Scan Range Limit No limit 003F C3 ret D5 0 Scan Range Limit No limit D4 0 Auto Increment Off D3 0 Auto Trig...

Page 52: ...vert equ 0302h Convert Register 0303 adclo equ 0303h A D Data Low Register 0304 adchi equ 0304h A D Data High Register 0309 clrflg equ 0309h Clear Flags Register 030A parlo equ 030Ah Parallel Port Data Low Register 030B parhi equ 030Bh Parallel Port Data High Register 030C dac0lo equ 030Ch D A Channel 0 Data Low Register 030D dac0hi equ 030Dh D A Channel 0 Data High Register 030E dac1lo equ 030Eh ...

Page 53: ... equ 0304h A D Data High Register 0309 clrflg equ 0309h Clear Flags Register 030A parlo equ 030Ah Parallel Port Data Low Register 030B parhi equ 030Bh Parallel Port Data High Register 030C dac0lo equ 030Ch D A Channel 0 Data Low Register 030D dac0hi equ 030Dh D A Channel 0 Data High Register 030E dac1lo equ 030Eh D A Channel 1 Data Low Register 030F dac1hi equ 030Fh D A Channel 1 Data High Registe...

Page 54: ...033 C3 ret 0034 channel_read channel_read channel_read channel_read channel_read Used to read input channels AL Channel number 00h to 0Fh Carry flag reflects logic state of input signal upon exit Use conditional jump instructions JC or JNC as appropriate to control program flow after calling this subroutine Carry 1 if selected input ON Carry 0 if selected input OFF 0034 52 push dx 0035 8A C8 mov c...

Page 55: ...off Used to turn an output channel OFF AL Channel Number If an input channel is specified nothing happens 005A 53 push bx 005B 51 push cx 005C 52 push dx 005D BB 7FFF mov bx 7FFFh Setup initial mask position 0060 8A C8 mov cl al Use channel as rotate counter 0062 D3 EB shr bx cl Rotate right to align mask 0064 BA 030A mov dx parlo Fetch existing state of ports 0067 ED in ax dx 0068 23 C3 and ax bx...

Page 56: ... Register 0300 status equ 0300h Status Register 0301 select equ 0301h Channel Select Register 0302 convert equ 0302h Convert Register 0303 adclo equ 0303h A D Data Low Register 0304 adchi equ 0304h A D Data High Register 0309 clrflg equ 0309h Clear Flags Register 030A parlo equ 030Ah Parallel Port Data Low Register 030B parhi equ 030Bh Parallel Port Data High Register 030C dac0lo equ 030Ch D A Cha...

Page 57: ...CT96 7 does not provide interrupt vector CPU will internally generate type code 13 001B B8 0000s mov ax vector Point data segment register to 001E 8E D8 mov ds ax interrupt vector area 0020 C7 06 0034 0046r mov word ptr ds 34h offset isr 0026 C7 06 0036 0000s mov word ptr ds 36h seg isr 002C B8 0000s mov ax data Point data segment register to 002F 8E D8 mov ds ax variable storage area 0031 C3 ret ...

Page 58: ...dx parlo Read parallel port 0051 ED in ax dx Additional processing code is inserted here if desired This could include mathematic manipulation data storage limit checks etc 0052 isr_exit 0052 BA FF22 mov dx eoi Issue a Non Specific End Of Interrupt 0055 B8 8000 mov ax 8000h command to 80188 interrupt controller 0058 EF out dx ax 0059 1F pop ds Restore CPU registers 005A 5A pop dx 005B 58 pop ax 00...

Page 59: ...rd for single ended input mode Disconnect cable from connector J1 Use a shorting jumper to short pins 1 and 3 on connector J1 This applies 0 000 volts AGND to channel 0 Using a program to continuously read channel 0 adjust the ZERO pot until the reading cen ters on 0000H Attach the voltmeter to the voltage source and adjust per the table below to the calibration voltage appropriate for the input r...

Page 60: ...nel 0 Adjust Z0 pot until voltage is exactly 10 0000V Write 07FFH to channel 0 If using 5V range adjust G0 pot until voltage is exactly 4 997559V If using 10V range adjust G0 pot until voltage is exactly 9 995117V Channel 1 Connect the voltmeter to channel 1 on connector J2 positive lead red to pin 8 negative lead black to pin 7 Write 0800H to channel 1 Adjust Z1 pot until voltage is exactly 10 00...

Page 61: ... supply to connector J2 positive to pin 5 ground to pin 4 Connect the milliammeter to connector J2 positive lead red to pin 6 negative lead black to pin 7 This effectively creates a 0 ohm current loop Turn G0 pot fully clockwise until it clicks This could be up to 30 turns Turn Z0 pot fully clockwise until it clicks This could be up to 30 turns Write 07FFH to channel 0 Measure the current flow Cal...

Page 62: ...7 4 VL 12CT96 7 Analog Digital I O Card ...

Page 63: ...In Address P27 A01 In Address P28 A09 In Address P29 A00 In Address P30 A08 In Address P31 WR In Write Mem or I O P32 RD In Read Mem or I O P33 IORQ In I O Address Select P34 MEMRQ Memory Address Select P35 IOEXP In I O Expansion P36 BHE MEMEX In Byte High Enable Mem Expansion P37 INTRQ1 Out Interrupt Request 1 P38 ALE Address Latch Enable P39 STATUS1 CPU Status 1 P40 STATUS0 CPU Status 0 P41 BUSA...

Page 64: ...E38 D11 Data E39 D18 Data E40 D10 Data E41 D17 Data E42 D09 Data E43 D16 Data E44 D08 Data E45 GND LogicGround E46 MASTER 16 Master 16 Bit E47 IRQx Out InterruptRequest E48 AENx AddressEnable E49 BE1 Byte Enable 1 E50 BE3 Byte Enable 3 E51 BE0 Byte Enable 2 E52 BE2 Byte Enable 2 E53 MEM16 Memory16 Bit E54 GND LogicGround E55 M IO Memory or I O E56 W R Write or Read E57 DMAIOW DMA I O Write E58 DMA...

Page 65: ...VL 12CT96 7 Analog Digital I O Card 8 3 VL 12CT96 7 Parts Placement Reference ...

Page 66: ...27 P29 P31 P33 P35 P37 P39 P41 P43 P45 P47 P49 P51 E13 E13 E15 E15 E17 E17 E19 E19 E21 E21 E23 E23 E25 E25 E27 E27 E29 E29 E31 E31 E33 E33 E35 E35 E37 E37 E39 E39 E41 E41 E43 E43 E45 E45 E47 E47 E49 E49 E51 E51 E53 E53 E55 E55 E57 E57 E59 E59 E61 E61 E63 E63 E65 E65 E67 E67 E69 E69 P3 E15 E19 E21 E23 12V STD32P E14 E14 E16 E16 E18 E18 E20 E20 E22 E22 E24 E24 E26 E26 E28 E28 E30 E30 E32 E32 E34 E34...

Page 67: ...R RD A3 2 3 4 6 1 5 7 8 9 19 18 17 16 15 14 12 13 1 1 U36 P1296B AD_HI SCNVT AD_LO EQ CT_WR ST_RD AD_INT P_INT 2 3 4 6 1 5 7 8 9 19 18 17 16 15 14 12 13 1 1 U28 P1296C RD 5 E59 IO16 DIR BD0 BD1 BD4 BD6 BD7 M_DLY BUSY DONE 8 RP15G DA_A DA_B DA_LO P_RD BHE RST PLO_WR PHI_WR 12BIT P_RD 1 3 2 4 V8 2 RP5A P47 RST 5V P36 RST 5 BHE VCC P13 P11 P14 GND D0 D1 D2 D3 D4 GND P9 P7 2 18 1 6 7 8 9 5 4 3 11 12 1...

Page 68: ... 3 5 2 4 6 V7 R17 R C CD4 CD5 CD0 CD1 CD2 CD3 CD9 CD10 CD11 CD12 CD13 CD14 CD15 1 1 5 2 3 5 6 11 10 14 13 4 7 9 12 U23 XX257 CD8 CD 0 15 CD15 CD15 CD15 BD15 1 1 5 2 3 5 6 11 10 14 13 4 7 9 12 U17 XX257 CD6 CD7 CD7 CD11 CD10 13 4 3 1 2 1 5 1 4 U19A XX221 CLR 5 BD7 MCLK NC M_DLY INC_EN CH_WR CLR M_DLY 2 3 4 6 1 5 7 8 9 19 18 17 16 15 14 12 13 1 1 U25 P1296D MCLK CH0 TP2 TP1 CH0 1 3 2 4 V2 CH0 DA0V M...

Page 69: ...D11 1 3 5 7 9 11 13 15 17 19 23 21 25 27 29 31 33 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 J3 2 RP6A 3 RP6B 4 RP6C 5 RP6D MD4 MD5 MD6 MD7 MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MO3 MO5 2 3 1 4 5 9 12 1 0 1 3 6 8 11 U11 XX126 MO2 MO4 PHI_WR MO12 MO11 MO10 MO9 MO8 BD3 BD4 BD5 BD6 BD7 BRST BD0 BD1 BD2 BD3 BD4 BD5 BD6 LD0 LD1 LD2 LD3 LD4 LD5 LD6 3 2 1 13 14 17 18 8 7 4 19 16 15 12 9 6 5 1 1 U20 XX373 ...

Page 70: ...35 100 µf 6 3V electrolytic radial Inductors L1 L3 10 µh 250 mH Inductor Integrated Circuits M1 HPR105 U1 INA103KP U5 U6 U14 4558 U2 XTR110 optional U3 U4 U10 U11 74HC126 U7 U8 DG408 U9 74HCT74 U12 ADS7804BP VL 12CT96 only ADS7805BP VL 12CT97 only U13 REF102AP U15 DAC7802KP U16 U17 U23 U24 74HCT257 U18 74HCT174 U19 74HCT221 U20 74HCT373 U21 U29 74ACT240 U30 U22 74ACT273 U25 PEEL18CV8 25 IP1296D Re...

Page 71: ...ional R8 R12 R15 1M Ω 1 1 8W R9 R11 1K Ω 0 1 1 8W R10 2 4K Ω 0 1 1 8W R13 R14 249 Ω 1 1 8W R16 3 3K Ω 1 1 8W R17 4 75K Ω 1 1 8W R18 9 53K Ω 1 1 8W RP1 RP4 1K Ω 4 resistor SIP RP7 RP8 RP10 10K Ω 4 resistor SIP RP5 RP6 RP9 P11 RP15 10K Ω 7 resistor SIP RP16 10K Ω 5 resistor SIP VR1 VR3 500 Ω trim pot 15 turn VR2 VR4 100K Ω trim pot 25 turn VR5 50K Ω trim pot 15 turn VR6 10K Ω trim pot 15 turn Semico...

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