4-6
VL-12CT96/7 Analog & Digital I/O Card
Analog Input Read Registers
Status Register
STATUS — 0300H
7
6
5
4
3
2
1
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Figure 4-9. Status Register
The STATUS register is a read register which contains the status of the VL-12CT96/7. It can be read
at any time to determine if an A/D conversion is complete, or if a parallel port interrupt is pending.
D7 — Busy.
This bit is set to “1” when an A/D conversion is currently in progress. This bit comes directly
from the A/D converter BUSY signal and resets to “0” automatically when the A/D conversion is
complete.
D6 — Done.
This bit is set to “1” when an A/D conversion has completed. It indicates that data is
available to be read from the ADCLO and ADCHI registers. When interrupts are enabled, the A/D
interrupt request signal goes active when Done is set.
The Done bit is reset to “0” when the ADCHI register is read (or it may be reset by writing to the
CLRFLG register).
D5 — Not Used.
This bit has no function on the VL-12CT96/7.
D4 — Settling Delay.
This bit is reset to “0” while the settling delay set by jumper V7 is in progress. The
bit is set to “1” at all other times. It is intended for factory use only.
D3, D2 — Not Used.
These bits have no function on the VL-12CT96/7. They will always read as “0”.
D1 — Parallel Port Interrupt Request.
Status bit indicating that a parallel port interrupt request is
pending. This bit changes from 0 to 1 when specific parallel port signal conditions are met as
determined by jumper V13. This bit changes from 1 to 0 when either PARLO or PARHI registers are
read.
Registers — Analog Input Registers
Summary of Contents for VL-12CT96
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