4-12
VL-12CT96/7 Analog & Digital I/O Card
Parallel Port Registers
Signal Direction
The VL-12CT96/7 parallel port signals are bidirectional. When the system is powered up, or a system
reset occurs, all of the channels are reset to inputs which causes the signal lines to go high.
Channels can be used as outputs by writing 0 or 1 to the appropriate bit in the PARHI or PARLO
register. Writing a 1 enables the open collector driver causing the signal line to go low. Writing a 0
tri-states the open collector driver, allowing the pull-up resistor to pull the signal line high.
Channels can be used as inputs by writing 0 to the appropriate bit in the PARHI or PARLO register.
Input status of the signal line can then be read by reading the same bit. Channels that are used as
inputs may be read at any time, but they must never have a 1 written to them. When writing to ports
which include both input and output channels, be certain to reset the bits corresponding to input
channels to 0.
Parallel Port Data High Register
Channel 1 (PARHI) — 030BH
7
6
5
4
3
2
1
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Figure 4-17. Parallel Port Data High Register
D7-D0 — MOD0-MOD7.
Data written to this register is driven onto the parallel port data signals MD0*–
MD7* on connector J3. This is an inverted data port; when a bit is set to 1 the signal line is driven low,
when a bit is reset to 0 the signal line is driven high.
Data read from this register returns the current
inverted input state of the parallel port signals. However, if a 1 has been written to a particular bit
position, that signal line is set to an output. Data will always read as 1 in this case. Please note:
D7=MOD0, D0=MOD7.
Parallel Port Data Low Register
Channel 1 (PARLO) — 030AH
7
6
5
4
3
2
1
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Figure 4-18. Parallel Port Data Low Register
D7-D0 — MOD8-MOD15.
Data written to this register is driven onto the parallel port data signals MD8*–
MD15* on connector J3. This is an inverted data port; when a bit is set to 1 the signal line is driven
low, when a bit is reset to 0 the signal line is driven high.
Data read from this register returns the
current inverted input state of the parallel port signals. However, if a 1 has been written to a particular
bit position, that signal line is set to an output. Data will always read as 1 in this case. Please note:
D7=MOD8, D0=MOD15.
Registers — Parallel Port Registers
Summary of Contents for VL-12CT96
Page 2: ...ii VL 12CT96 7 Analog Digital I O Card ...
Page 26: ...2 20 VL 12CT96 7 Analog Digital I O Card ...
Page 32: ...3 6 VL 12CT96 7 Analog Digital I O Card ...
Page 62: ...7 4 VL 12CT96 7 Analog Digital I O Card ...
Page 65: ...VL 12CT96 7 Analog Digital I O Card 8 3 VL 12CT96 7 Parts Placement Reference ...
