Lion (VL-EPMe-42) Programmer’s Reference Manual
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Programming Information for Hardware
Interfaces
Processor WAKE# Capabilities
The following devices can wake up the processor using the PCIE_WAKE# signal to the SoC:
Ethernet port 1 controller
Minicard (when always-powered)
FPGA via either a Digital I/O or AUX connector GPIO
The following nine USB devices can wake up the processor using the in-band SUSPEND
protocol:
The 2 On-Board USB 3.0 Ports
Any of the 4 CBR-4005 Paddleboard USB Ports
Either of the 2 PCI104/Express “A” Connector (1-Blade) USB Ports
Minicard (when always-powered)
Watchdog Timer
A Watchdog timer is implemented within the FPGA. When triggered, the Watchdog timer can set
a status bit, generate an interrupt and/or hit the push-button-reset. The Watchdog timer
implements a 1-255 second timeout.
The Watchdog time out is set in an 8-bit register (WDT_VAL). When the Watchdog is enabled,
the WDT_VAL will start to count down. If the Watchdog is enabled and whenever WDT_VAL
is zero, the Watchdog is triggered (so a non-zero value must be written before enabling the
watchdog). Software must periodically write a non-zero value to WDT_VAL to prevent this
trigger. The value written should always be 1 greater than the desired timeout value due to a 0-1
second error band. Values written should be from 2-255 because a 1 could cause an immediate
trigger); that is, the actual timeout is WDT_VAL seconds with a -1 second to 0 second error
band.
The Watchdog control/status register(s) have bits for the following:
Watchdog enable/disable (disabled by default)
Watchdog timeout status (This is cleared when the Watchdog is disabled or when a new
value is written to WDT_VAL. Writing WDT_VAL would be the interrupt-acknowledge.)
Watchdog interrupt IRQ select (from the same list of eight interrupts supported on the LPC
SERIRQ)
Interrupt enable
Board reset enable (when set, the board will be reset when the Watchdog timer expires).
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