FPGA Registers
Lion (VL-EPMe-42) Programmer’s Reference Manual
20
AUXDIR – AUX GPIO Direction Control Register
This register controls the direction of the eight AUX GPIO signals.
This reset depends on the state of the FPGA_PSEN signal. If FPGA_PSEN is a ‘0’ then the reset is the
power-on and Platform Reset. If FPGA_PSEN is a ‘1’ then this register is only reset at power-on.
Table 17: AUXDIR – AUX GPIO Direction Control Register
Bit
Identifier
Access
Default
Description
7-0
DIR_GPIO[8:1]
R/W
0
Sets the direction of the AUX GPIOx lines. For each bit:
0 – Input
1 – Output
AUXPOL – AUX GPIO Polarity Control Register
This register controls the polarity of the eight AUX GPIO signals.
This reset depends on the state of the FPGA_PSEN signal. If FPGA_PSEN is a ‘0’ then the reset is the
power-on and Platform Reset. If FPGA_PSEN is a ‘1’ then this register is only reset at power-on.
Table 18: AUXPOL – AUX GPIO Polarity Control Register
Bits
Identifier
Access
Default
Description
7-0
POL_GPIO[8:1]
R/W
0
Sets the polarity of the AUX GPIOx lines. For each bit:
0 – No inversion
1 – Invert
Note:
This impacts the polarity as well as the interrupt status
edge used.
AUXOUT – AUX GPIO Output Control Register
This register sets the AUX GPIO output value. This value will only set the actual output if the GPIO
direction is set as an output. Reading this register does not return the actual input value of the GPIO (use the
AUXIN register for that). As such, this register can actually be used to detect input/output conflicts.
This reset depends on the state of the FPGA_PSEN signal. If FPGA_PSEN is a ‘0’ then the reset is the
power-on and Platform Reset. If FPGA_PSEN is a ‘1’ then this register is only reset at power-on.
Table 19: AUXOUT – AUX GPIO Output Control Register
Bits
Identifier
Access
Default
Description
7-0
OUT_GPIO[8:1]
R/W
0
Sets the AUX GPIOx output values. For each bit:
0 – De-asserts the output (0 if polarity not-inverted, 1 if inverted)
1 – Asserts the output (1 if polarity not-inverted, 0 if inverted)
