FPGA Registers
Lion (VL-EPMe-42) Programmer’s Reference Manual
26
FANTACHLS, FANTACHMS – Fan Tach Status Registers
These registers contain the number of fan tach output samples over a one-second sampling period. The
value is always valid after the fan speed stabilizes and is updated every 1 second (after a delay of 1 second).
Currently, only the lower 10-bits have a valid tach reading (that is, the upper 6 bits will always be zero).
The fan tach count should never overflow in the one second period, but it if does, the value will “stick” at
0x03FF.
The board can handle up at least a 10,000 RPM fan with a fan tach output of up to four uniform pulses per
revolution. The duty cycle of the fan tach output pulse can be as low as 25% (typically they are very close
to 50%). The conversion to RPM is as follows:
RPM = (FANTACH x 60) / PPR
Where…
FANTACH - the 16-bit register reading
PPR – fan tach pulses per revolution (typically either 1, 2, or 4)
Reset type is n/a.
Table 29: FANTACHLS – FANTACH Status Register Least Significant Bits
Bits
Identifier
Access
Default
Description
7-0
FANTACH[7:0]
RO
N/A
Least significant eight bits of FANTACH.
Read this register first since it latches the value for the most
significant eight bits.
Table 30: FANTACHMS – FANTACH Status Register Most Significant Bits
Bits
Identifier
Access
Default
Description
7-0
FANTACH[15:8]
RO
N/A
Most significant eight bits of FANTACH.
Read this register after reading FANTACHLS.
Integrator’s Note:
The FANTACHLS register must be read first. It will latch a copy of the MS bits so that when
FANTACHMS is read, it is based on the same 16-bit value. This assumes that a 16-bit word read
on the LPC bus reads the even (LS) address before the odd (MS) address.
