FPGA Registers
Lion (VL-EPMe-42) Programmer’s Reference Manual
18
Miscellaneous FPGA Registers
MISCR1 – Miscellaneous Control Register #1
This is a register in the always-on power well of the FPGA. It holds its state during sleep modes and can
only be reset by a power cycle. This is a placeholder register for features like pushing the power-button and
also for software initiated resets should those be needed. This register is only reset by the main power-on
reset since it must maintain its state in Sleep modes (for example, S3).
Table 14: MISCR1 – Misc. Control Register #1
Bits
Identifier
Access
Default
Description
7-2
Reserved
RO
000000
Reserved. Writes are ignored; reads always return 0.
1
AUX_PSEN
R/W
0
AUX GPIO Bank I/O Power Enable
0 – The AUX GPIO bank will be powered down in sleep modes (only
power in S0)
1 – The AUX GPIO bank will not be powered down in sleep modes and
the configuration will remain.
The GPIO bank power switch is controlled by the “OR” of the S0 power
control signal and
FPGA_PSEN
.
Note: Some register resets are conditional on the state of
AUX_PSEN
0
MINI_PSDIS
R/W
0
Minicard 3.3 V power disable
0 – Minicard 3.3 V power stays on always (this is normally how
minicards operate if they support any Wake events)
1 – Minicard 3.3 V power will be turned off when not in S0 (in sleep
modes).
The Minicard 3.3 V power switch is controlled by the “OR” of the S0
power control signal and the inverse of MINI_PSDIS.
MISCR2 – Miscellaneous Control Register #2
This is a register in the always-on power well of the FPGA. It holds its state during sleep modes and can
only be reset by a power cycle. It is primarily used for control signals for the always-powered Ethernet
controllers and the USB hubs. This register is only reset by the main power-on reset since it must maintain
its state in sleep modes (for example, S3).
