VersaLogic Lion VL-EPMe-42 Reference Manual Download Page 1

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Programmer’s
Reference
Manual

REV. May 2018

Lion

(VL-EPMe-42)

Intel

Core™-based Single Board Computer with

Dual Ethernet, Video, USB, SATA, Serial I/O,

Digital I/O, Trusted Platform Module security,

Counter/Timers, Mini PCIe, mSATA, SPX, and

PCIe/104™ OneBank™ Interface

Summary of Contents for Lion VL-EPMe-42

Page 1: ...al REV May 2018 Lion VL EPMe 42 Intel Core based Single Board Computer with Dual Ethernet Video USB SATA Serial I O Digital I O Trusted Platform Module security Counter Timers Mini PCIe mSATA SPX and...

Page 2: ...made to ensure this document is error free VersaLogic makes no representations or warranties with respect to this product and specifically disclaims any implied warranties of merchantability or fitnes...

Page 3: ...Support The EPMe 42 support page contains additional information and resources for this product including Reference Manual PDF format Operating system information and software drivers Data sheets and...

Page 4: ...escriptions 8 Product Information Registers 8 BIOS and Jumper Status Register 9 Timer Registers 11 SPI Control Registers 14 SPI Data Registers 16 SPI Debug Control Register and mSATA PCIe Select Contr...

Page 5: ...Me 42 Hardware Reference Manual provides information on the board s hardware features including connectors and all interfaces EPMe 42 BIOS Reference Manual provides information on accessing and config...

Page 6: ...interrupt status is determined by the devices on this interface The interface supports two interrupts Thermal event and battery low interrupts Note The EPMe 42 also has two COM ports COM3 COM4 that ar...

Page 7: ...O Address Range Device Owner 2F8h 2FFh COM2 serial port default 3B0h 3DFh Legacy VGA registers 3F8h 3FFh COM1 serial port default 400h 47Fh ACPI Power management reserved 500h 5FFh PCH GPIO reserved...

Page 8: ...es to make word access possible in software but the LPC bus still splits the accesses into two 8 bit accesses FPGA address range 0xC80 to 0xCBF 64 byte window The three 8254 timers only require four b...

Page 9: ...1 D0 Description C80 0 Platform PLED PRODUCT_CODE PCR Product Code PLED C81 1 n a REV_LEVEL EXTEMP CUSTOM BETA PSR Rev Ext Tmp Custom Beta C82 2 Platform BIOS_JMP BIOS_OR BIOS_SEL LED_DEBUG WORKVER 0...

Page 10: ...gital I O registers used on other products C9B 1B n a 0 0 0 0 0 0 0 0 Reserved for Digital I O registers used on other products C9C 1C n a 0 0 0 0 0 0 0 0 Reserved for Digital I O registers used on ot...

Page 11: ...PICR Temperature HW Monitor Interrupt Mask and Control CB1 31 Platform BATTLOW 0 0 0 ISTAT_BATTLOW ISTAT_EVENT ISTAT_THERM ISTAT_ALERT TEMPISTAT Temperature Interrupt Mask and Status CB2 32 Platform I...

Page 12: ...ult Description 7 PLED R W 0 Drives the programmable LED on the paddleboard 0 LED is off default 1 LED is on can be used by software 6 0 PRODUCT_CODE RO 0010101 Product Code for the EPMe 42 0x15 Table...

Page 13: ...leased and is still in a working state 0 FPGA is released 1 FPGA is in a working state not released 2 RESERVED RO N A Reserved Writes are ignored reads always return 0 1 GPI_JMP RO N A Status of the G...

Page 14: ...lected Comments 0 X don t care OFF Primary Configuration Switch selects the BIOS BIOS_SEL ignored 0 X don t care ON Secondary Configuration Switch selects the BIOS BIOS_SEL ignored 1 1 OFF Primary BIO...

Page 15: ...0 Interrupts disabled 1 Interrupts enabled 6 4 IRQSEL 2 0 R W 000 8254 Timer interrupt IRQ select in LPC SERIRQ 000 IRQ3 001 IRQ4 010 IRQ5 011 IRQ10 100 IRQ6 101 IRQ7 110 IRQ9 111 IRQ11 3 RESERVED RO...

Page 16: ...est signal When INTRTEST 1 this signal is used for the timer input control instead of the external ICTC3 signal When INTRTEST 0 this is ignored 0 deasserted 1 asserted 3 RESERVED RO 0 Reserved Writes...

Page 17: ...on signal GCTC3 is enabled Always set to 0 when configuring timer modes Set to a 1 if using external clocking It can be turned on and off when using internal clocking 4 TM45MODE R W 0 Mode to set tim...

Page 18: ...edge on which valid data will be read 0 Data is read on rising edge 1 Data is read on falling edge 5 4 SPILEN 1 0 R W 00 Determines the SPI frame length This selection works in manual and auto slave s...

Page 19: ...les the selected IRQ to be activated by a SPI device that is configured to use interrupt capability SPX I F interrupts are not supported on this product 0 IRQ s are disabled for SPI operations 1 the I...

Page 20: ...e select to begin an SPI bus transaction Data is sent according to the LSBIT_1ST setting When LSBIT_1ST 0 the MSbit of SPIDATA3 is sent first and received data will be shifted in the LSbit of the sele...

Page 21: ...led by an FPGA pull down 011 Force PCIe mode on the Minicard 100 Force mSATA mode on the Minicard 101 Undefined same as 000 110 Undefined same as 000 111 Undefined same as 000 Note When the Minicard u...

Page 22: ...1 The AUX GPIO bank will not be powered down in sleep modes and the configuration will remain The GPIO bank power switch is controlled by the OR of the S0 power control signal and FPGA_PSEN Note Some...

Page 23: ...enabled On 1 Ethernet Phy controller is disabled Off 3 RESERVED RO 0 s Reserved Writes are ignored Reads always return 0 2 RESERVED RO 0 s Reserved Writes are ignored Reads always return 0 1 RESERVED...

Page 24: ...IO Polarity Control Register Bits Identifier Access Default Description 7 0 POL_GPIO 8 1 R W 0 Sets the polarity of the AUX GPIOx lines For each bit 0 No inversion 1 Invert Note This impacts the polar...

Page 25: ...arity inverted AUXIMASK AUX GPIO Interrupt Mask Register This is the interrupt mask registers for the AUX GPIOs and the interrupt enable selection The reset type is Platform Reset because interrupts a...

Page 26: ...n Table 23 AUXMODE1 AUX I O Mode Register Bit Identifier Access Default Description 7 MODE_GPIO8 R W 0 GPIO 8 Mode 0 GPIO I O 1 ICTC3 input 6 MODE_GPIO7 R W 0 GPIO 7 Mode 0 GPIO I O 1 ICTC4 input 5 MO...

Page 27: ...7 110 IRQ9 111 IRQ11 3 Reserved RO 0 Reserved Writes are ignored reads always return 0 2 RESET_EN R W 0 Enable the Watchdog to assert the push button reset if it fires 0 Watchdog will not reset the bo...

Page 28: ...cond to 0 second error band Table 25 WDT_VAL Watchdog Control Register Bits Identifier Access Default Description 7 0 WDT_VAL 7 0 R W 0x00 Number of seconds before the Watchdog fires By default it is...

Page 29: ...always return 0 FANCON Fan Control Register The fan is always off in any sleep mode When the processor comes out of a sleep state this register must be setup again since it will be reset to default b...

Page 30: ...ery close to 50 The conversion to RPM is as follows RPM FANTACH x 60 PPR Where FANTACH the 16 bit register reading PPR fan tach pulses per revolution typically either 1 2 or 4 Reset type is n a Table...

Page 31: ...7 IRQEN R W 0 Temperature interrupt enable disable 0 Interrupts disabled 1 Interrupts enabled 6 4 IRQSEL 2 0 R W 000 Temperature interrupt IRQ select in LPC SERIRQ 000 IRQ3 001 IRQ4 010 IRQ5 011 IRQ1...

Page 32: ...ys return 0 3 ISTAT_BATTLOW RW C N A Battery Low interrupt status A read returns the interrupt status Writing a 1 clears the interrupt status This bit is set to a 1 on a transition from de asserted to...

Page 33: ...Bits Identifier Access Default Description 7 IRQEN R W 0 UART interrupt enable disable 0 Interrupts disabled 1 Interrupts enabled 6 4 IRQSEL 2 0 R W 001 UART Interrupt IRQ Select in LPC SERIRQ 000 IR...

Page 34: ...ntifier Access Default Description 7 IRQEN R W 0 UART interrupt enable disable 0 Interrupts disabled 1 Interrupts enabled 6 4 IRQSEL 2 0 R W 000 UART interrupt IRQ select in LPC SERIRQ 000 IRQ3 COM2 D...

Page 35: ...tform Note The values shown are for the default BIOS configuration Table 35 UARTMODE1 UART MODE Register 1 Bits Identifier Access Default Description 7 6 Reserved RO 00 Reserved Writes are ignored rea...

Page 36: ...ly for the 16x UART clock This bit must be set to use rates above 115 200 and may require custom software Reset type is Platform Note The values shown are for the default BIOS configuration Table 36 U...

Page 37: ...DT_VAL When the Watchdog is enabled the WDT_VAL will start to count down If the Watchdog is enabled and whenever WDT_VAL is zero the Watchdog is triggered so a non zero value must be written before en...

Page 38: ...ates a transaction to the specified slave device In manual mode the slave select is controlled by the user and any number of data frames can be sent The user must command the slave select high to comp...

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