Ublox SARA-N2 Series, System Integration Manual

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SARA-N2 / N3 series - System integration manual
UBX-17005143 - R13 System description Page 10 of 95
C1-Public
Function Pin name Modules Pin No I/O Description Remarks
System PWR_ON SARA-N3 15 I Power-on input Internal pull-up.
Provide a test point on this pin for diagnostic purpose.
See section
1.6.1 , 1.6.2 for functional description.
See section 2.3.1 for external circuit design-in.
RESET_N All 18 I HW reset input Internal pull-up.
Provide a test point on this pin for diagnostic purpose.
See section
1.6.3 for functional description.
See section 2.3.2 for external circuit design-in.
VSEL SARA-N3 21 I Voltage selection Input to select the operating voltage of the
V_INT
supply output, voltage domain of UARTs, I2C, GPIOs.
V_INT = 1.8 V (typical), if VSEL pin is connected to GND
V_INT = 2.8 V (typical), if VSEL pin is unconnected
See section 1.6.4 for functional description.
See section 2.3.3 for external circuit design-in.
Antenna ANT All 56 I/O Cellular RF
input/output
50

nominal characteristic impedance.
Antenna circuit affects the RF performance and
compliance of the device integrating the module with
applicable required certification schemes.
See section
1.7.1 for description and requirements.
See section 2.4.1 for external circuit design-in.
ANT_BT SARA-N3 59 I/O Bluetooth RF
input/output
50  nominal characteristic impedance.
See section 1.7.2 for description and requirements.
See section 2.4.2 for external circuit design-in.
ANT_DET All 62 I Input for antenna
detection ANT_DET not supported by SARA-N2 modules.
ADC input usable for antenna detection function.
See section
1.7.3 for functional description.
See section 2.4.3 for external circuit design-in.
SIM VSIM All 41 O SIM supply
output Supply output for external SIM / UICC
See section
1.8 for functional description.
See section 2.5 for external circuit design-in.
SIM_IO All 39 I/O SIM data Data line for communication with external SIM,
operating at
VSIM voltage level.
Internal 4.7 k  pull-up to VSIM .
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
SIM_CLK All 38 O SIM clock Clock for external SIM, operating at VSIM voltage level.
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
SIM_RST All 40 O SIM reset Reset for external SIM, operating at VSIM voltage level
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
UART
(main)
RXD All 13 O Data output Circuit 104 (RXD) in ITU-T V.24
SARA-N2 series modules:
• Supporting AT communication, FOAT and FW
upgrade via dedicated tool
•
VCC voltage level
SARA-N3 series modules:
• Supporting AT communication and FOAT
• V_INT voltage level
Provide a test point on this pin for diagnostic purpose.
See section
1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.