LISA-U1 series - System Integration Manual
3G.G2-HW-10002-3
Preliminary
System description
Page 59 of 125
Name
Description
Remarks
SPI_MISO
SPI Data Line.
Master Input, Slave Output
Module Output.
Idle high.
Shift data on rising clock edge (CPHA=1).
Latch data on falling clock edge (CPHA=1).
MSB is shifted first.
SPI_MOSI
SPI Data Line.
Master Output, Slave Input
Module Input.
Idle high.
Shift data on rising clock edge (CPHA=1).
Latch data on falling clock edge (CPHA=1).
MSB is shifted first.
Internal active pull-up to V_INT (1.8 V) enabled.
SPI_SCLK
SPI Serial Clock.
Master Output, Slave Input
Module Input.
Idle low (CPOL=0).
Up to 26 MHz supported.
Internal active pull-down to GND enabled.
SPI_MRDY
SPI Master Ready to transfer data control line.
Master Output, Slave Input
Module Input.
Idle low.
Internal active pull-down to GND enabled.
SPI_SRDY
SPI Slave Ready to transfer data control line.
Master Input, Slave Output
Module Output.
Idle low.
Table 23: SPI interface signals
The SPI interface pins ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F).
Higher protection level could be required if the lines are externally accessible on the application board.
Higher protection level can be achieved by mounting an low capacitance (i.e. less than 10 pF) ESD
protection (e.g. EPCOS CA05P4S14THSG varistor array) on the lines connected to these pins.
1.9.4.1
IPC communication protocol overview
The module runs as an SPI slave, i.e. it accepts AT commands on its SPI interface without specific configuration.
The SPI-device shall look for all upper-SW-layers like any other serial device. This means that LISA-U1 series
modules emulate all serial logical lines: the transmission and the reception of the data are similar to an
asynchronous device.
Two additional signals (
SPI_MRDY
and
SPI_SRDY
) are added to the SPI lines to communicate the state of
readiness of the two processors: they are used as handshake signals to implement the data flow.
The function of the
SPI_MRDY
and
SPI_SRDY
signals is twofold:
For transmitting data the signal indicates to the data receiver that data is available to be transmitted
For receiving data the signal indicates to the transmitter that the receiver is ready to receive data
Due to this setup it is possible to use the control signals as interrupt lines waking up the receiving part when
data is available for transfer. When the handshaking has taken place, the transfer occurs just as if it were a
standard SPI interface without chip select functionality (i.e. one master - one slave setup).
SPI_MRDY
is used by the application processor (i.e. the master) to indicate to the module baseband processor
(i.e. the slave) that it is ready to transmit or receive (IPC master ready signal), and can also be used by the
application processor to wake up the module baseband processor if it is in idle mode.
SPI_SRDY
line is used by the module baseband processor (i.e. the slave) to indicate to the application processor
(i.e. the master) that it is ready to transmit or receive (IPC slave ready signal), and can also be used by the module
baseband processor to wake up the application processor if it is in hibernation.
