TYANO S7126, Manual

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37
DDR4 Memory Configuration
This section highlights the memory configuration for DDR4 DIMM population for Ice
Lake processor based systems.

Note #1 – rank sparing, ADDDC, channel mirroring, hemisphere modes
and 2LM not supported with Intel SGX

There should be at least one DDR4 DIMM per socket

If only one DIMM is populated in a channel, then populate it in the slot
furthest away from CPU of that channel

Always populate the DIMM with the higher electrical loading on a channel
in DIMM0 followed by DIMM1

Channel 0’s on each memory controller (A/E/C/G) must be populated with
same total capacity per channel (if populated)

Channel 1’s on each memory controller (B/F/D/H) must be populated with
same total capacity per channel (if populated)