Tomcat i7221 S5150
Chapter 3: BIOS Setup
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However, the manufacturer of your parallel port peripheral may have designated a preferred
parallel port mode for the device in question. In that case, it's best to follow their
recommendation.
SPP
/ SPP+EPP1.9/ECP/ECP+EPP1.9/Standard/SPP+EPP1.7/ECP+EPP1.7
ECP Mode Use DMA
This BIOS feature determines which DMA channel the parallel port should use when it is in
ECP mode.
The ECP mode uses the DMA protocol to achieve data transfer rates of up to 2.5 Mbits/s and
provides symmetric bidirectional communications. For all this, it requires the use of a DMA
channel.
By default, the parallel port uses DMA Channel 3 when it is in ECP mode. This works fine in
most situations.
This feature is provided just in case one of your add-on cards requires the use of DMA
Channel 3. In such a case, you can use this BIOS feature to force the parallel port to use the
alternate DMA Channel 1.
Please note that there is no performance advantage in choosing DMA Channel 3 over DMA
Channel 1 or vice versa. As long as either Channel 3 or Channel 1 is available for your parallel
port to use, the parallel port will be able to function properly in ECP mode.
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3.7 Power Management Setup
Options related to power management can be altered through the following:
ACPI Suspend Type
This option specifies the method to be used hibernation. The options are as follows.
•
S1 (POS) (Power On Suspend):
In this method, the processor does not execute
instructions but remains connected to the bus; the processor preserves the state
and content of its internal registers, along with the dynamic context of the memory.
Only information about devices qualified as suitable to be woken up from hibernation
is kept by the processor. When a waking up event occurs, the devices that can wake
up the system force all the peripherals to be relinked.
•
S3 (STR) (Suspend To RAM): In this method, the processor does not execute
instructions. The state and content of the processor's internal registers is stored in
RAM along with the dynamic context of the memory. Information about devices
qualified as suitable to be woken up from hibernation is also stored in RAM. When a
waking up event occurs, the devices that can wake up the system restore the
