Toshiba TDP-D1, Service Manual

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Figure 1 shows a generic approach to resolving input signal design considerations.
Figure 1. Analog RGB Input Circuit
Place L1 as close to the connector pin as possible to reduce reflections. The stray capacitance is
not shown. R1 is the 75  termination r

esistance, and its ground point needs to be placed as close as
possible to the input connector signal ground return. L2 becomes the balancing inductor for the high
impedance subsystem. The undesignated diodes represent the ESD protection devices. C1 is used to
match the impedance of the final input circuit to 75  at the frequency of interest, and to reduce

signal bandwidth to remove frequencies above the input data rate. The inductor and capacitor values
for each individual system will vary with layout and component choices. Typically, L1 and L2 are
specified as 40  @ 100Mhz and C1 as 12pF.

Sync on Green (SOG)
Another carry -over from the past is Sync on Green (SOG). In this situation, an added input to
the display processor is available. This needs to be connected to the green channel of the analog
RGB, which adds capacitance to the green channel. Doing so typically affects L2 or C1 (shown in
Figure 1) for the green channel only. As one might believe, matching the SOG subsystem
capacitance improves system performance. The suggested circuit configuration shown in Figure 1
creates a specific element of phase delay. This delay is not harmful if all three channels have similar
delay numbers. Any variation in the delay from one channel to the next greater than 2% of the
maximum pixel cycle time influences apparent phase noise and can create improper color
reproduction. This is especially true for the green channel, where the SOG burden influences its
delay differently from the red or blue channels.