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Preliminary

THCV245A_Rev.0.90_E

THine Electronics, Inc.

Security C

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6.35 Lock / Re-Lock Sequence

Lock and re-lock sequence are as follows. V-by-One® HS automatically shifts into lock status from initial

status or unlock status caused by external noise under appropriate parameter set condition.

Figure 22.

Lock Sequence

Figure 23.

Re-Lock Sequence

Table 54.

Lock / Re-Lock Sequence specification

THCV45A .REG(R_PLL_SNRST)

THCV245A.REG(R_VX1_SNRST)

THCV245A.TX0P/TX0N (,TX1P/TX1N)

Training pattern

Main-Link Rx.LOCKN

tLT

tTPLL0

Rx Main-Link LOCK time

Main-Link Rx as Sub-Link Master

polling (worst case)

LOCKN=H

LOCKN=L

Polling Interval

One

poling

Normal Operation

tTNP1

THCV245A LOCK Sequence

Main-Link Rx.LOCKN

Main-Link Rx as Sub-Link Master

polling (worst case)

LOCKN=L

LOCKN=H

One

poling

Polling Interval

THCV241-Q.TX0P/TX0N (,TX1P/TX1N)

Training pattern

Rx Main-Link LOCK time

Normal Operation

LOCKN=H

LOCKN=L

Polling Interval

One

poling

THCV245A Re-LOCK Sequence

Normal output

tTNP0

tTNP1

Symbol

Parameter

Min

Typ

Max

Unit

tTNP0

LOCKN=H to Training pattern output delay

tTNP1

LOCKN=L to Data pattern output delay

1200

F(OUT)

Summary of Contents for THCV245 A

Page 1: ...tor camera module from remote ECU via GPIO UART or 1Mbps 2 wire serial interface Several fault and error detection function including CRC provides hardware functional safety design 2 Features MIPI CSI...

Page 2: ...ance mode 16 6 5 6 V by One HS output Odd Even swap 17 6 5 7 V by One HS output Drivability 17 6 5 8 V by One HS output Low Frequency mode 17 6 5 9 Target Pixel clock 18 6 6 Blanking period restrictio...

Page 3: ...ield BET operation and output from GPIO 51 6 30 CMOS IO Input noise Filter 52 6 31 CMOS output drive strength 52 6 32 CKO reference clock buffer output 53 6 33 Soft Reset 54 6 34 Power On Sequence 56...

Page 4: ...29 28 27 26 25 24 23 22 21 VDDM SCL SDA AIN INT VDDL PDN0 VDDIO MSSEL LOCKN 31 RD3P THCV245A VDDA 20 32 RD3N TX0N 19 33 RD1P 41 EXPGND TX0P 18 34 RD1N TX1N 17 35 RCKP TX1P 16 36 RCKN TEST 15 37 RD0P T...

Page 5: ...input Negative polarity If external LOCKN connection is used it is supposed to be connected to Rx LOCKN w ith a 30k pull up resistor GPIO0 7 B GPIO0 GPIO1 8 B GPIO1 GPIO2 9 B GPIO2 GPIO3 10 B GPIO3 MS...

Page 6: ...also can report interrupt events caused by change of GPIO inputs and internal statuses such as CRC error 6 2 Reference clock supply Reference clock supply CKI is required since MIPI CSI 2 clock strea...

Page 7: ...put mapping sw ap select MIPI standard format lane assignment used on RX1P RX1N input The same setting as R_RX_LANE_SEL0 2 3 is prohibited 2 h1 0x1026 3 2 R_RX_LANE_SEL2 2 R W MIPI Data Lane RX2P RX2N...

Page 8: ...normal mode LOCKN of Receiver is open drain Transmitter side needs pull up resistor When an application omits HTPDN LOCKN signal should only be considered with HTPDN pulled low by Receiver Vcc Tx side...

Page 9: ...MPRF Figure 4 MPRF Main Link PRivate Format Addr h Bits Register w idth R W Description Default 0x1000 0 R_VX1_LANE 1 R W V by One HS output lane number setting 0 1lane 1 2lanes 1 h1 0x1001 6 4 R_OUT...

Page 10: ...4 1st Y 4 2nd 0 RAW 4 1st RAW 4 1st Cb U 4 Y 4 1st V by One HS_D 19 Cb U 3 Cr V 3 Y 3 1st Y 3 2nd 0 RAW 3 1st RAW 3 1st Cb U 3 Y 3 1st V by One HS_D 18 Cb U 2 Cr V 2 Y 2 1st Y 2 2nd 0 RAW 2 1st RAW 2...

Page 11: ...by One HS_D 19 RAW 3 1st B 3 B 0 R 3 1st 0 RAW 5 1st RAW 1 1st V by One HS_D 18 RAW 2 1st B 2 0 R 2 1st 0 RAW 4 1st RAW 0 1st V by One HS_D 17 RAW 1 1st B 1 0 R 1 1st 0 RAW 3 1st 0 V by One HS_D 16 RA...

Page 12: ...W 1 1st RAW 7 1st RAW 3 1st RAW 9 1st RAW 5 1st V by One HS_D 16 0 RAW 4 1st RAW 0 1st RAW 6 1st RAW 2 1st RAW 8 1st RAW 4 1st V by One HS_D 15 0 0 0 RAW 5 1st RAW 1 1st RAW 7 1st RAW 3 1st V by One H...

Page 13: ...RAW 3 3rd 0 Cb U 3 3rd Y 3 3rd V by One HS_D 2 Cr V 2 Cb U 2 Cb U 2 RAW 2 3rd 0 Cb U 2 3rd Y 2 3rd V by One HS_D 1 Cr V 1 Cb U 1 Cb U 1 RAW 1 3rd 0 Cb U 1 3rd Y 1 3rd V by One HS_D 0 Cr V 0 Cb U 0 Cb...

Page 14: ...1st R 3 3rd RAW 5 1st RAW 5 3rd RAW 1 3rd V by One HS_D 2 RAW 2 5th R 2 1st 0 R 2 3rd RAW 4 1st RAW 4 3rd RAW 0 3rd V by One HS_D 1 RAW 1 5th R 1 1st 0 R 1 3rd RAW 3 1st RAW 3 3rd 0 V by One HS_D 0 R...

Page 15: ...7 3rd RAW 3 3rd V by One HS_D 2 RAW 6 1st RAW 6 3rd RAW 2 3rd RAW 4 3rd RAW 0 3rd RAW 6 3rd RAW 2 3rd V by One HS_D 1 RAW 5 1st RAW 5 3rd RAW 1 3rd RAW 3 3rd 0 RAW 5 3rd RAW 1 3rd V by One HS_D 0 RAW...

Page 16: ...n Emission and High Immunity Resistance mode are available Immunity resistance strength is HS 2 b11 HS 2 b10 Radiated emission level is HS 2 b11 HS 2 b10 Table 12 V by One HS Low Radiation Emission or...

Page 17: ...y Mode setting Addr h Bits Register w idth R W Description Default 0x1052 0 R_ML_OE_SWAP 1 R W V by One HS 1st Pixel Start Timing Select 0 1st pixel assign on lane0 1 1st pixel assign on lane1 1 h0 Ad...

Page 18: ...ow Power mode to High Speed mode and from High Speed mode to Low Power mode In addition for THCV245A when MIPI data rate per lane is slower than 160Mbps horizontal blanking period length must meet bel...

Page 19: ...target Pixel clock F target by 8 accuracy as below formula for most cases 20 130 FeedBack Divider x 1 FBDiv 2nd Output Divider x 1 OutDiv2 x 1 OutDiv1 1st Output Divider 1 7 1 7 F Out 10 133 3MHz PLL...

Page 20: ...zontal active is rather large and total pixel data rate is rather slow as described in previous table condition minimum allowed F OUT setting is not equal to F target if Spread Spectrum function is ac...

Page 21: ...p60fps YUV422 27 0x21 0x00 0x00 0x00 0x64 0x01 7 1080p30fps YUV422 37 125 0x18 0x00 0x00 0x00 0x64 0x01 8 720p120fps RAW 27 0x21 0x00 0x00 0x00 0x44 0x01 9 1080p60fps RAW 37 125 0x18 0x00 0x00 0x00 0x...

Page 22: ...on Default 0x100F 0 R_PLL_SET_MODE 1 R W PLL setting mode 0 PLL Auto setting mode 1 PLL Manual setting mode 1 h0 0x100E 7 6 R_CKI_FREQ 2 R W PLL Auto setting input frequency choice 2 h0 Reserved 2 h1...

Page 23: ...equency divider setting values R_DIVVAL on Address 0x1010 to meet V by One HS standard 30kHz 0 5 are exemplified below Table 22 V by One HS output SSCG R_DIVVAL setting examples Addr h Bits Register w...

Page 24: ...rror can be detected with CRC THCV245A generates and sends check value to receiver For usage of CRC function the counterpart V by One receiver must have installed CRC monitor like THCV242 Table 23 V b...

Page 25: ...THCV236 Q Table 24 V by One HS output MIPI Packet Header bridge setting Figure 6 MIPI Packet Header V by One HS output bridge timing alternative Addr h Bits Register w idth R W Description Default 0x...

Page 26: ...6 V by One HS_D 5 V by One HS_D 4 V by One HS_D 3 V by One HS_D 2 V by One HS_D 1 V by One HS_D 0 THCV236 HFSEL 0 THCV236 D 31 THCV236 D 30 THCV236 D 29 THCV236 D 28 THCV236 D 27 THCV236 D 26 THCV236...

Page 27: ...CV242 Q default 1 Low pulse Low active 1 h0 0x1007 3 R_VS_MODE 1 R W V by One HS VSYNC output timing mode 0 MIPI FS FE timing direct use mode THCV242 Q default 1 internally generated timing mode 1 h0...

Page 28: ...1 R W V by One HS Hsync polarity 0 High pulse High active THCV242 Q default 1 Low pulse Low active 1 h0 0x1009 1 0 R_HS_MODE 2 R W V by One HS HSYNC output timing mode 00 01 MIPI LS LEtiming direct u...

Page 29: ...Vertical blanking period FE LINE 1 in Vblank LINE 2 in Vblank LINE k in Vblank V by One HS PCLK MIPI FE Internal HSYNC generation counter Internally generated V by One HS HSYNC For example R_HSYNC_PO...

Page 30: ...FE_SYNCEN 2 b00 setting is required to bridge both MIPI Frame Start and Frame End Short Packet R_VSYNC_POL 1 b0 setting is required to connect THCV242 THCV236 Q connection is only supported where HFSE...

Page 31: ...HS_D 1 V by One HS_D 0 THCV236 HFSEL 0 THCV236 D 31 THCV236 D 30 THCV236 D 29 THCV236 D 28 THCV236 D 27 THCV236 D 26 THCV236 D 25 THCV236 D 24 THCV236 D 23 THCV236 D 22 THCV236 D 21 THCV236 D 20 THCV2...

Page 32: ...ve Device ID setting can be changed from default value by register setting Table 28 2 wire serial I F Device ID select by register setting Pin Name Pin type Description AIN 27 I Select Slave Address 0...

Page 33: ...directly access THCV245A local register by 2 wire serial I F Figure 13 Host to THCV245A local register access configuration Figure 14 2 wire serial I F write to THCV245A local register protocol Figur...

Page 34: ...23 1 d1 MS 0x004C 0x00CC 7 0 R_2WIRE_WD_TIM 8 RW 2 w ire WDT time 64 R_2WIRE_WD_TIM 7 0 1 2WIRE WDT offset time tOSC 8 d255 MS Sub Link Master Master Slave or Slav e Addr h Addr h Bits Register w idth...

Page 35: ..._SLINK_MODE setting Table 31 Sub Link Master protocol basic setting Master Master Slave or Slave Addr h Addr h Bits Register width R W Description Default related 0x0004 1 0 R_SLINK_MODE 2 RW Sub Link...

Page 36: ...to be divided into 0x00 and 0xFE commands by 8bit Sub Address restriction Table 32 Sub Link Word Address control setting Under 1Byte Word Address access operation 0x00FE bit0 1 b1 1Byte access to 0xF...

Page 37: ...A internal local register control and monitoring on 2 wire Set Trigger mode1 Figure 17 Host MPU to 2 wire slave devices connected to Sub Link Slave via THCV245A access configuration Sub Link Block 2 w...

Page 38: ..._2WIRE_CLKSEN Sub Link Master side register 0x0042 bit0 selects whether 2 wire serial slave of Sub Link Master perform clock stretching When R_2WIRE_CLKSEN 1 Sub Link Master device waits HOST MPU unti...

Page 39: ...ce address if target self addr access to Sub Link Slave inside register else access to remote side 2 w ire serial Slave devices externally connected to Sub Link slave 7 h00 M 0x0040 0 R_2WIRE_WR 1 RW...

Page 40: ...t of R_INT_SLINK_TMOUT Table 34 Sub Link WDT setting Master Master Slave or Slav e Addr h Addr h Bits Register w idth R W Description Default related 0x0018 0x0098 7 5 reserved 3 0x0018 0x0098 4 R_SLI...

Page 41: ...is informed from Sub Link Slave to Sub Link Master Detectable interrupts both on Sub Link Master and Slave are as follows IC Internal event except Sub Link Internal register Checksum error 2 wire acc...

Page 42: ...with THCV242 or THCV244 as Sub Link Master communication THCV245A as Sub Link Slave GPIO1 0 Sub Link Polling bridges output from THCV242 or THCV244 GPIO Through Mode and GPIO3 2 Sub Link Polling bridg...

Page 43: ...lection interval Figure 19 Host MPU to Sub Link Slave Register via THCV245A access configuration Remote UART bridge is supported with Sub Link Polling GPIO input output Remote UART Tx and Rx bridge ba...

Page 44: ...Polling is compatible w ith THCV236 GPIO Through mode 4 h0 0x103E 7 4 R_GPIO_OUT 4 R W GPIO0 3 Output Data Register 3 GPIO3 2 GPIO2 1 GPIO1 0 GPIO0 4 h0 0x103E 3 0 R_GPIO_OEN 4 R W GPIO0 3 Input Outp...

Page 45: ...GPIO and Sub Link 4 h0 0x105D 3 0 R_ERR_SEL2 4 R W Internal Selected Error2 output to GPIO and Sub Link 4 h0 Master Master Slave or Slav e Addr h Addr h Bits Register w idth R W Description Default re...

Page 46: ...K_ERR_SEL1 of Sub Link Slave R_SLINK_ERR_SEL1 of Sub Link Master h04 h05 h06 h07 h08 h09 h0A R_INT_LOCKN 1 b0 h0B R_INT_HTPDN 1 b0 h0C R_INT_SLAVESIDE 1 b0 h0D R_INT_EXTI2C_ACSEND 1 b0 h0E 1 b0 R_INT_...

Page 47: ...RR_CTL_MSK 4 0 MIPI R_INT_FS 3 0 R_INT_FS_ON_CLR 3 0 R_INT_FS_MSK_R 3 0 MIPI R_INT_FE 3 0 R_INT_FE_ON_CLR 3 0 R_INT_FE_MSK_R 3 0 Main Link R_DHNDL_INT R_DHNDL_INT_CLR R_DHNDL_INT_MSK GPIO R_GPIO_INT_D...

Page 48: ...ated module and not included in Sub Link Module so that R_INT_EXTERNAL factor must be set as No mask in order to report those MIPI Main Link GPIO and other Interrupt factor to remote Sub Link Master F...

Page 49: ...0 R_GS_SEL_G 8 R W BIST Gradient Setting Green 00 Black FF Green 8 hff 0x1063 7 0 R_GS_SEL_B 8 R W BIST Gradient Setting Blue 00 Black FF Blue 8 hff 0x1064 3 0 R_CURSOH 11 8 4 R W BIST Cursor position...

Page 50: ...Frame2 01 White raster 1 11 4 1 checker 1 02 Black raster 2 12 4 1 checker 2 03 Red raster 3 13 2 1 checker 1 04 Green raster 4 14 2 1 checker 2 05 Blue raster 5 15 1 1 checker 1 06 Horizontal color...

Page 51: ...ine Sub Link Slave device also has BET function mode Sub Link Slave device receives the data stream and checks bit errors Note that Sub Link Slave device must be set this mode prior to Sub Link Master...

Page 52: ...O Input Signal Noise Fillter Setting for GPIO1 0 No Fillter n Filtering Glitch Signal w hen Pulse Width is Less than tOSC n 2 ns 4 h4 0x104C 3 0 R_IOFLT_RANGE5 4 R W CMOS IO Input Signal Noise Fillter...

Page 53: ...Security C 53 67 6 32 CKO reference clock buffer output CKO reference clock buffer output can be configurable by 2 wire access to internal register Table 50 CKO setting Addr h Bits Register w idth R W...

Page 54: ...1 R W Softw are Reset for V by One HS TX 0 Softw are Reset Active 1 Softw are Reset Release Vx1HS TX Normal Operation 1 h0 0x1021 0 R_C_SNRST 1 R W MIPI CSI 2 Soft Reset 0 Reset 1 Reset Release MIPI...

Page 55: ...ODE 0 R_CKI_FREQ R_MIPI_MULT R_VX1_LANE R_OUTPUT_FMT R_HFSEL R_RX_LANE_SEL_EN else if R_PLL_SET_MODE 1 R_PLL_SETTING 47 0 R_DIVVAL on both R_PLL_SET_MODE 0 and R_PLL_SET_MODE 1 R_SPREAD R_DISABLE_SSCG...

Page 56: ...PLL setting parameters are completely written t1 t5 t6 tLT TX0P TX0N TX1P TX1N tTPLL0 REG R_TX_SNRST Soft Reset mustbe released after all Vx1HS TX settingparemeters written andPLL locked To force REG...

Page 57: ...CV245A TX0P TX0N TX1P TX1N Training pattern Main Link Rx LOCKN tLT tTPLL0 Rx Main Link LOCK time Main Link Rx as Sub Link Master polling worst case LOCKN H LOCKN L Polling Interval One poling Normal O...

Page 58: ...Max Unit Supply Voltage VDDH VDDIO VDDB 0 3 4 V Supply Voltage VDD12 VDDM VDDOP VDDL VDDA 0 3 1 6 V LVCMOS Input Voltage 0 3 VDDIO 0 3 1 V MIPI Input Voltage 0 3 VDDM 0 3 2 V CML Transmitter Output Vo...

Page 59: ...1 8V Drive PDN1 1 14 22 mA ICCW12_3 Main link FHD 60Hz HDR MPRF RAW10 Distribution Sub Link active PDN0 1 PDN1 1 MIPI 1 2Gbps x4Lane V by One HS 4 0Gbps x2Lane 140 176 mA ICCW12_11 Main link 720p 30fp...

Page 60: ...CMOS Low Level Output Voltage 0 0 45 V VIHIO VILIO LVCMOS High Level Input Voltage LVCMOS Low Level Input Voltage Symbol Parameter Condition Min Typ Max Unit ILEAK mipi D PHY pin Leak Current Pow erDo...

Page 61: ...00 400 500 mV R_ML _PRE 1 0 00 0 R_ML _PRE 1 0 01 R_ML _DRV 1 0 00 01 40 50 60 R_ML _PRE 1 0 10 R_ML _DRV 1 0 00 80 100 120 R_ML _PRE 1 0 00 VDDA VTOD V R_ML _PRE 1 0 01 VDDA 1 5 VTOD V R_ML _PRE 1 0...

Page 62: ...ifferential Output Voltage R_BDCZ_TERM_ 1 0 2 b10 R_BDCZ_DRIVE_ 1 0 2 b10 Diff 100ohm terminated 200 300 400 mV VBOC CML Bi Directional Buffer Common Output Voltage R_BDCZ_TERM_ 1 0 2 b00 R_BDCZ_DRIVE...

Page 63: ...igure 25 CML Transmitter tTRF 11 3 CML B directional Buffer AC Specifications Table 64 CML B directional Buffer AC Specifications Symbol Parameter Condition Min Typ Max Unit UI Unit Interval 0 833 12...

Page 64: ...STOPcondition 0 26 ns tBUF Bus free time betw een a STOP and START condition 0 5 us tSP Pulse w idth of spikes w hich must be suppressed by the input filter at R_IOFLT_RANGE 2 5 50 ns tPDS Required w...

Page 66: ...onics Inc THine Electronics Inc Security C 66 67 12 Package TOP VIEW SIDE VIEW 1 PIN INDEX BOTTOM VIEW 1 0 40 0 20 0 05 Max 0 20 0 65 0 90 Max 5 00 5 00 3 70 3 70 0 40 40 10 11 20 21 30 31 Unit mm EXP...

Page 67: ...the product is specified as a product conforming to the demands and specifications of IATF16949 the Specified Product in this data sheet THine accepts no liability whatsoever for any product other th...

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