Preliminary
THCV245A_Rev.0.90_E
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6.33 Soft Reset
Soft Reset is available by 2-wire access to internal register.
PLL and V-by-One® HS initial statuses are reset state; therefore Soft Reset is supposed to be released in
accordance with appropriate sequence: PLL Soft Reset release => V-by-One® HS TX Soft Reset release.
Table 51.
Soft Reset register
Also, change of PLL and V-by-One® HS parameters automatically cause Soft Reset without any touch on
R_PLL_SNRST nor R_TX_SNRST, whose temporary reset time length can be defined by R_PLL_CTERM and
R_TX_CTERM respectively.
Table 52.
Automatic Soft Reset of PLL and V-by-One® HS recovery time control
Addr(h)
Bits
Register
w idth
R/W
Description
Default
0x1005
[0]
R_PLL_SNRST
1
R/W
Softw are Reset for PLL
0:Sof tw are Reset Active
1:Sof tw are Reset Release (PLL Normal Operation)
1'h0
0x1006
[0]
R_TX_SNRST
1
R/W
Softw are Reset for V-by-One® HS TX
0:Sof tw are Reset Active
1:Sof tw are Reset Release (Vx1HS TX Normal Operation)
1'h0
0x1021
[0]
R_C_SNRST
1
R/W
MIPI CSI-2 Sof t Reset
0:Reset
1:Reset Release (MIPI CSI-2 Normal Operation)
1'h1
0x1022
[0]
R_DCLKSNRST
1
R/W
Digital logic Clock Soft Reset
0:Reset
1:Reset Release (Digital logic Clock Normal Operation)
1'h1
0x1023
[0]
R_MCLKSNRST
1
R/W
MIPI Clock Sof t Reset
0:Reset
1:Reset Release (MIPI Clock Normal Operation)
1'h1
0x10FF
[7:0]
R_REGSNRST
8
R/W
Register Sof t Reset
AA:Reset
others:Reserved
8'h00
Addr(h)
Bits
Register
w idth
R/W
Description
Default
0x105B
[7:0]
R_PLL_CTERM
8
R/W
PLL parameter change
automatic reset recovery time length
00 Disable(Disable Auto Sof t Reset)
01 1*256*tOSC (typ.3.2us)
02 2*256*tOSC (typ.6.4us)
03 3*256*tOSC (typ.9.6us)
:
:
FE 254*256*tOSC (typ.812.8us)
FF 255*256*tOSC (typ.816us)
8'h55
0x105C
[7:0]
R_TX_CTERM
8
R/W
V-by-One® HS parameter change
automatic reset recovery time length
00 Disable(Disable Auto Sof t Reset)
01 1*256*tOSC (typ.3.2us)
02 2*256*tOSC (typ.6.4us)
03 3*256*tOSC (typ.9.6us)
:
:
FE 254*256*tOSC (typ.812.8us)
FF 255*256*tOSC (typ.816us)
8'h55