Preliminary
THCV245A_Rev.0.90_E
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6.5.9 Target Pixel clock
Target pixel clock for transmission is defined by a formula below.
Relationship between used packet and byte mode packet transfer potential is determined by output format
(from Table 4) and whether Auto or Manual Byte-mode setting is used or not in Byte-mode setting (Table 10).
6.6
Blanking period restriction under low MIPI data-rate environment
First of all, horizontal blanking period must meet minimum required length as MIPI standard defines to change
MIPI data lane from Low Power mode to High Speed mode and from High Speed mode to Low Power mode.
In addition for THCV245A, when MIPI data-rate per lane is slower than 160Mbps, horizontal blanking period
length must meet below rule.
Another alternative is simply to use 160Mbps and higher MIPI data-rate because cases to use below 160Mbps
must be the cases of [nmp]=4 so that MIPI data-rate can be arranged to be higher by using [nmp]=1 or 2
configuration.
Byte mode packet total
[dmp] = MIPI Data-rate
[nmp] = MIPI lane number
Used packet in output format
[nvx1] = V-by-One® HS lane number
[bmvx1] = V-by-One® HS Byte Mode
Total pixel data-rate = [dmp] x [nmp]
[dmp] x [nmp]
Byte mode packet total
Used packet in output format
[bmvx1] x8 x x [nvx1]
[PCLK.target] = Pixel clock target for V-by-One® HS per lane = [F(target)]
[PCLK.target] =
= [F(target)]
= [PCLK.target] x [bmvx1] x8 x x [nvx1]
