Preliminary
THCV245A_Rev.0.90_E
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6.7
PLL setting
PLL setting is required. For manual setting, R_PLL_SET_MODE is supposed to be set 1 (Manual mode) from
default value 0. PLL Manual mode setting set R_PLL_SETTING[47:0] is related with CKI frequency.
Figure 5.
Reference clock supply basic method
PLL_SETTING[47:0] must be selected proper to meet below constraints.
Table 16.
PLL constraints table
Pixel clock frequency made by PLL is calculated as below.
Actual Pixel clock, F(OUT) frequency must be equal or greater than ideal target Pixel clock, F(target) by 8%
accuracy as below formula for most cases.
20-130
FeedBack Divider
x 1/FBDiv
2nd Output Divider
x 1/OutDiv2
x 1/OutDiv1
1st Output Divider
1-7
1-7
F(Out)
10-133.3MHz
PLL Conf iguration
F(VCO)
F(CKI)
PFD
VCO
500-1300MHz
10-40MHz
symbol
discription
condition
min
typ
max
unit
F(CKI)
CKI input f requency
-
10
-
40
MHz
FBDiv
FeedBack Divider value
-
20
-
130
-
OutDiv1
1st Output Divider value
(OutDiv1 must be >= OutDiv2)
-
1
-
7
-
OutDiv2
2nd Output Divider value
(OutDiv1 must be >= OutDiv2)
-
1
-
7
-
F(VCO)
VCO frequency
-
500
-
1300
MHz
F(OUT)
PLL output pixel clock frequency
-
10
-
133.3
MHz
Hactive=< 1280pixels
and [dmp]x[nmp] < 500Mbps
1280 <Hactive=< 1920pixels
and [dmp]x[nmp] < 800Mbps
1920 <Hactive=< 3840pixels
and [dmp]x[nmp] <1500Mbps
otherw ise
0
0
8
%
D
F
| R_SPREAD|
-
8
%
Allow ed error betw een F(target) vs F(OUT)
