THine CEL SerDes THCV235-Q, Manual

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THCV235-Q_THCV236-Q_Rev.3.40_E
Copyright
©
2016 THine Electronics, Inc.
THine Electronics, Inc.
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Security E
Table 1. Pin Sharing Description (THCV235-Q)
Sub-Link State →
Sub-Link
Power Down
Low Speed Data
Bridge Mode
2-wire serial
I/F Mode
Sub-Link
Master/Slave →
- Master Slave Master Slave
PDN1 0 1 1 1 1
HTPDN/SUBMODE * 1 1 0 0
LOCKN/MSSEL * 0 1 0 1
BET/GPIO1 0 0 0 * *
RF/BETOUT
RF
BETOUT
(*2)
COL0/INT/GPIO2 COL0 COL0 COL0 INT GPIO2
(*4)
COL1/SD0 COL1 SD0(input) SD0(output)
(*6)
SD0(SDA) SD0(SDA)
PRE/SD1 PRE SD1(input) SD1(output)
(*6)
SD1(SCL) SD1(SCL)
CMLDRV/SD2/AIN0/GPIO3 CMLDRV SD2(input) SD2(output)
(*6)
AIN0 GPIO3
(*5)
LATEN/SD3/AIN1/GPIO4
-
(*1)
SD3(output)
(*6)
SD3(input) AIN1 GPIO4
(*5)
LATEN
(*3)
SSEN/GPIO0 SSEN SSEN SSEN GPIO0
(*4)
GPIO0
(*4)
BET/GPIO1 BET BET BET GPIO1
(*4)
GPIO1
(*4)
MAINMODE/TCMP MAINMODE TCMP
HFSEL/TCMN HFSEL TCMN
LOCKN/MSSEL LOCKN MSSEL
HTPDN/SUBMODE HTPDN SUBMODE
*1 There is no function. LVCMOS IO has input state. Must be fixed at 0 or 1 input.
*2 When Field BET mode (Main-Link or Sub-Link), it functions as BETOUT output.
*3 When Field BET mode (Main-Link or Sub-Link), it functions as LATEN input.
*4 Programmable GPIO input is default on register setting.
*5 Through GPIO open-drain output is default on register setting.
*6 Low Speed Data Bridge Mode output is LVCMOS push pull buffer.