THCV235-Q_THCV236-Q_Rev.3.40_E
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©
2016 THine Electronics, Inc.
THine Electronics, Inc.
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Security E
Field BET Operation
In order to help users to check validity of CML serial line (Main-Link and Sub-Link), the THCV235-Q and
THCV236-Q have an operation mode in which they act as a bit error tester (BET). In Main-Link Field BET
mode, the THCV235-Q internally generates test pattern which is then serialized onto the Main-Link CML line.
The THCV236-Q also has BET function mode. The THCV236-Q receives the data stream and checks bit errors.
The generated data pattern is then 8b/10b encoded, scrambled, and serialized onto the CML channel. As for the
THCV236-Q, the internal test pattern check circuit gets enabled and reports result on a certain pin named
BETOUT. In Sub-Link Field BET mode, Sub-Link Master device internally generates test pattern which is then
serialized onto the Sub-Link CML line. Sub-Link Slave device also has BET function mode. Sub-Link Slave
device receives the data stream and checks bit errors.
Note that Sub-Link Slave device must be set this mode
prior to Sub-Link Master device.
Pattern check result is output from BETOUT pin of the Sub-Link Slave device.
The BETOUT pin goes LOW whenever bit errors occur, or it stays HIGH when there is no bit error.
In Main-Link Field BET mode, user can select two kinds of check result, latched result or NOT latched result
by setting LATEN pin input. The latched result is reset by setting LATEN=0. In Sub-Link Field BET mode, only
latched result is available. In order to reset the latched result, please once turn off the power and entry Sub-Link
Field BET from power on sequence.
LATEN/SD3/AIN1/GPIO4 pin (THCV235-Q) and LATEN/SD3/AIN1/GPIO0 pin (THCV236-Q) function as
LATEN in Field BET mode (Main-Link or Sub-Link).
It is not possible to realize Main-Link Field BET and Sub-Link Field BET at the same time.
Table 16.
Main-Link Field BET Operation Settings
THCV235-Q/236-Q
Common Setting
THCV236-Q
Setting
Condition
PDN0 PDN1 SUBMODE
BET BET_SEL
LATEN
Main-Link
Sub-Link
Output Latch
Select
1
0
-
1
(*1)
0
(*3)
0
Field BET
Operation
Power
Down
NOT Latched Result
1
Latched Result
1
1
1
(*1)
0
(*3)
0
Normal
Operation
NOT Latched Result
1 Latched Result
0
1
(*2)
0
(*4)
0
NOT Latched Result
1
Latched Result
*1 Pin setting
*2 THCV235-Q: Register setting (0x53 bit1), THCV236-Q: Pin setting
*3 When PDN0=1, PDN1=0 and BET=1 or PDN0=1, PDN1=1, SUBMODE=1 and BET=1, BET_SEL is set to 0 automatically.
*4 Register setting (0x53 bit0, Default 0)
Table 17.
THCV236-Q Main-Link Field BET Result
BETOUT
Output
L
Bit Error Occurred
H
No
Error
