THCV235-Q_THCV236-Q_Rev.3.40_E
Copyright
©
2016 THine Electronics, Inc.
THine Electronics, Inc.
11/68
Security E
D25/GPIO4 19
B
D25 : Pixel Data Output
GPIO4 : General Purpose Input/Output when SUBMODE=0,
MSSEL=0 and RXDEFSEL=0.
When GPIO4 is used as Open-Drain Output, it must be connected
with a pull-up resistor to VDD.
When GPIO4 is used as push pull output or input, no external
component is required.
D24/GPIO3 20
B
D24 : Pixel Data Output
GPIO3 : General Purpose Input/Output when SUBMODE=0,
MSSEL=0 and RXDEFSEL=0.
When GPIO3 is used as Open-Drain Output, it must be connected
with a pull-up resistor to VDD. When GPIO3 is used as push pull
output or input, no external component is required.
D23-D0
21-24,27-31,33-39,
42-47,52,53
O
Pixel Data Output
DE
51
O
DE
Output
HSYNC
50
O
HSYNC
Output
VSYNC
48
O
VSYNC
Output
OE
63
IL
Output
Enable
0 : LVCMOS Output Disable (Hi-Z) except for HTPDN,
LOCKN when PDN1=0 and except for BETOUT when BET=1.
1 : LVCMOS Output Enable
BET
64
IL
Field
BET
entry
0 : Normal Operation
1 : Field BET Operation
RF/BETOUT 6
B RF : Output Clock Triggering edge select. See Figure 20.
0 : Falling Edge
1 : Rising Edge
BETOUT : Field BET Result Output
RXDEFSEL
62
I
Internal Register Default Setting Select. See Table 44, Table 45
0 : for THCV231-Q
1 : for THCV235-Q
LFSEL
3
I
Low Frequency mode select
0 : Low Frequency mode Disable
1 : Low Frequency mode Enable
PDN1
2
IL
Sub-Link Power Down
0 : Power Down. Main-Link setting by external pin
1 : Normal Operation. Main-Link Setting by 2-wire serial I/F
PDN0
1
IL
Main-Link Power Down
0 : Power Down
1 : Normal Operation
TEST2
5
I
Test pin. Must be tied to Ground for normal operation.
TEST1
4
IL
Test pin. Must be tied to Ground for normal operation.
CAPOUT
56
PWR
Decoupling Capacitor Pin, 1.2V output.
CAPINA
59
PWR
Reference Input for Analog Circuit. Must be tied to CAPOUT.
VDD
49,41,32,25,16
PWR
1.7-3.6V Digital Power Supply Pin for LVCMOS I/O
AVDD
40
PWR
1.7-3.6V Analog Power Supply Pin for LDO
EXPGND
65
GND
Exposed Pad Ground. Must be tied to the PCB ground plane
through an array of vias.
CI : CML Input buffer , CB : CML Bi-directional buffer
I : LVCMOS Input buffer , IL : Low Speed LVCMOS Input buffer , O: LVCMOS Output buffer
B : LVCMOS Bi-directional buffer , BO : Open-Drain LVCMOS Bi-directional buffer
PWR : Power supply , GND : Ground
