6-6
Themis Computer
USPIIe-USB Hardware Manual
6.3.6
Software XIR
Software may initiate a reset equivalent to an Externally-Initiated-Reset (XIR) by
setting the SOFT_XIR bit in the UltraSPARC-II
e
Reset_Control Register (
Table 6-1
below). This bit will remain set until software clears it, to allow software to detect
the source of the reset.
6.4
UltraSPARC-II
e
Reset_Control_Register
The
UltraSPARC-II
e
reset_control_register
indicates the source of a reset
and provides control of software reset generation. It is located at 0x1FE.0000.F020.
Note:
Internal to the UltraSPARC-II
e
are the Watch Dog Reset (WDR) and Soft-
ware Initiated Reset (SIR). These two resets are initiated within the processor core
and affect only the processor.
Table 6-1.
UltraSPARC-II
e
Reset_Control_Register
Field
Bits
Value
Description
Type
Reserved
63:32
0
Reserved
R0
POR
31
*
a
Set if the last reset was due to the assertion of SYS_RESET_L
R/W1C
SOFT_POR
30
*
Setting to 1 causes a POR reset; stays set until software clears it
R/W
SOFT_XIR
29
*
Setting to 1 causes an XIR trap; stays set until software clears it
R/W
B_POR
28
*
Set if the last reset was due to the assertion of P_RESET_L
R/W1C
B_XIR
27
*
Set if the last reset was due to the assertion of an X_Reset_L
R/W1C
Reserved
26:0
*
Reserved
R0
a—The highest priority reset source has its bit set. Only the bits marked with “*” are set.
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com