xiii
Themis Computer
Table of Contents
List of Tables
Table 1-1
USPII
e
-USB Model Configurations ................................................................ 1-1
Table 1-2
Front-Panel DIN Settings................................................................................. 1-3
Table 2-1
CPU Speed Settings ......................................................................................... 2-1
Table 2-2
Memory Configurations................................................................................... 2-3
Table 2-3
Processor Specifications .................................................................................. 2-8
Table 2-4
Memory Specifications .................................................................................... 2-9
Table 2-5
USPII
e
-USB I/O Subsystem Specifications .................................................. 2-10
Table 2-6
Auxiliary Functions Specifications................................................................ 2-12
Table 2-7
USPII
e
-USB Operating Environmental Specifications ................................. 2-13
Table 2-8
USPII
e
-USB Non-operating Environmental Specifications.......................... 2-13
Table 2-9
Estimated Power Requirements ..................................................................... 2-13
Table 4-1
Universe II Miscellaneous Control Register (MISC_CTL)............................. 4-5
Table 4-2
Universe II Power-Up Options ........................................................................ 4-7
Table 4-3
PCI Configuration Base Address 0 Register (PCI_BS0)................................. 4-9
Table 4-4
PCI Configuration Base Address 1 Register (PCI_BS1)................................. 4-9
Table 4-5
VMEbus Fields for VMEbus Slave Image .................................................... 4-10
Table 4-6
PCI Bus Fields for VMEbus Slave Image ..................................................... 4-11
Table 4-7
Control Fields for VMEbus Slave Image ...................................................... 4-12
Table 4-8
PCI Bus Fields for PCI Bus Target Image..................................................... 4-13
Table 4-9
PCI Bus Fields for PCI Bus Target Images ................................................... 4-14
Table 4-10
Control Fields for PCI Bus Target Image ...................................................... 4-14
Table 4-11
PCI Bus Fields for Special PCI Bus Target Image ........................................ 4-15
Table 4-12
Control Fields for Special PCI Bus Target Image ......................................... 4-15
Table 4-13
Special PCI Target Image Register (Offset 188) ........................................... 4-16
Table 5-1
PLD Register Address Map ............................................................................. 5-2
Table 6-1
UltraSPARC-II
e
Reset_Control_Register ....................................................... 6-6
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