4-8
Themis Computer
USPIIe-USB Hardware Manual
The PCI Configuration Base Address 0 and Base Address 1 Registers’ offsets are
0x010 and 0x014, respectively. The registers specify the 4KB aligned base address
of the 4 KB Universe II register space on PCI. The power-up options determine if
the registers are mapped into Memory or I/O space.
.
SYSFAIL* Assertion
VCSR_SET
SYSFAIL
Asserted
VD[27]
VCSR_CLR
SYSFAIL
--
--
PCI Target IMAGE
LSI0_CTL
EN Disabled
VA[13]
LAS[0]
Memory
VA[12]
VAS
A16
VA[11..10]
LSI0_BS BS
0x0
VA[9..6]
LSI0_BD
BD
0x0
VA[5..2]
PCI Bus Size
b
MISC_STAT
LCLSIZE
32-bit
REQ64*
PCI CSR Image Space
PCI_CSR
BM
Disabled
VA[14]
PCI Register Access
PCI_BS0
PCI_BS1
SPACE
Refer to:
Table 4-3
and
Table 4-4
.
VA[1]
PCI Bus Size
c
MISC_STAT
LCLSIZE
32-bit
REQ64*
PCI CSR Image Size
PCI_CSR
BM
disabled
VA[14]
a—The LAS field will enable the PCI_CSR registers IOS or MS field if the EN FIELD of the LSIO_CTL register is set.
b—As per PCI 2.1 Specification, the PCI Bus Size is loaded on any RST* event.
c—Following the PCI 2.1 Specification, the PCI Bus Size is loaded on any RST* event.
Table 4-2.
Universe II Power-Up Options (Continued)
Option
Register
Field
Default
Pins
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