Index
Index-5
Themis Computer
PMC Module
Module 0
2-3
Module 1
2-6
Module 2
2-6
Module 3
2-6
Slot 0 connector
A-10
Slot 1, 32-Bit User I/O configuration
A-18
Slot 1, 64-Bit User I/O configuration
A-17
Slot 2, 32-Bit User I/O configuration
A-19
Slot 3, 0-Bit User I/O configuration
A-20
Polyswitch Vcc power fuse
2-7
POR
6-2
,
6-4
,
6-5
See also
Power-On-Reset
power fail signal
2-7
power management
5-4
power requirements
2-13
Power-On-Reset (POR)
5-4
,
6-2
,
6-5
power-up options
Universe II
4-7
P-Reset
6-3
,
6-4
printer port
1-10
processor
and memory subsystems
2-8
specifications
2-8
speeds
2-1
UltraSPARC-IIe
3-1
product registration
xxiv
Programmable Logic Device.
See
PLD
protocols
PS/2 and USB
C-3
PS/2–USB connector
1-3
,
A-8
pinouts
A-8
protocols
C-3
push-button reset (P-Reset)
6-4
,
A-11
R
RDFIFO
4-3
reader comment card
1-2
references, related
xxi
register access at power up
4-7
registering Your SPARC 5/64-2S2E
xxiv
registers
MISC_CTL
4-5
PLD
5-2
special PCI target image
4-16
registration, product
xxiv
related references
xxi
reset architecture
3-3
resets
6-1
control registers
6-6
Externally Initiated Reset (XIR)
6-3
power management
6-4
priorities
6-2
push-button (P-Reset)
6-4
,
A-11
request signals
6-2
Software Initiated Reset (SIR)
6-3
software POR
6-5
software XIR
6-6
sources
6-4
system and P-Reset
6-3
VMEbus
6-4
Watchdog (WDR)
6-3
RIC.
See
USPIIe-USB Reset, Interrupt, and
Clock
RJ45
1-10
RMW cycle
4-3
Round-Robin arbitration
4-6
RXFIFO
4-3
S
SCSI
controller
1-4
termination
1-4
,
1-6
SCSI Ports
Port A
2-3
,
2-7
connector
A-5
paddle board connector
A-23
paddle board connector pinouts
A-24
Ultra3 LVD
2-3
Port B
connector
A-5
Ultra3 LVD
2-3
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