3-4
Themis Computer
USPIIe-USB Hardware Manual
3.1.3
PCI-to-PCI Bridges
The USPII
e
-USB fans out the single 66-MHz/32-bit primary PCI bus (see
Figure 2-1
on page 2-2) into three secondary busses:
• Two 33-MHz/32-bit PCI busses using the Sun APB PCI-to-PCI interface chip
• One 33-MHz/64-bit PCI bus using the Intel 21154 PCI-to-PCI interface chip
One APB-based PCI bus is dedicated to data traffic to the VME bus through the Uni-
verse II PCI-to-VME bridge chip.
The second APB-based PCI bus is dedicated to remaining onboard devices through
the Sun Rio controller chip (see the following section "Sun Rio I/O Controller" on
page 3-5.
The “transparent” Intel-based PCI bus is dedicated to servicing disk traffic from the
SCSI controller and all I/O to the on-board PMC Module slot, and all other PMC
Modules on any PCM Carrier and TGA3D/3D+ Graphics boards that may be
installed in the second and third VME slots (see Appendix C, “Front Panel Dia-
grams”).
3.1.3.1 Advanced PCI Bridge (APB)
The USPII
e
-USB Advanced PCI Bridge (SME2411) interfaces directly with the
UltraSPARC-II
e
microprocessor and concentrates two (2), 32-bit, 33MHz PCI buses
into one 32-bit, 66-MHz PCI bus that interfaces directly with the UltraSPARC-II
e
.
The 66-MHz PCI-to-CPU bridge can achieve a peak bandwidth of 2 GBits/sec.
Within the USPII
e
-USB, the two 33-MHz PCI busses are referred to as PCIA and
PCIB.
3.1.3.2 Intel 21154 PCI-to-PCI Bridge
The Intel 21154 PCI-to-PCI bridge complies with
PCI Local Bus Specification
,
Revision 2.2, and has a 66-MHz/32-bit primary bus interface and a 33-MHz/64-bit
secondary interface.
The 21154 provides full support for delayed transactions, which enables the buffer-
ing of memory read, I/O, and configuration transactions. The 21154 has separate
posted write, read data, and delayed transaction queues with significant buffering
capability. In addition, the 21154 supports buffering of simultaneous, multiple,
posted write, and delayed transactions in both directions.
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