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7

Schematics and Bill of Materials

7.1

Schematics

+6V_IN

6V_IN

INHIBIT

+3.3V

+2.5V

+1.2V

+3.3V

+2.5V

+1.2V

VCC_BANK5_ADJ

+1.8V

VCC_BANK5_ADJ

+6V

+3.3V_USB

+6V

+6V

+5V

ADC

+6V

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

+6V

+3.3V

GND

+3.3V_USB

+1.2V

GND

GND

+3.3V_USB

GND

+3.3V_USB

+5V

ADC

VCC_BANK5_ADJ

+6V

+2.5V

JP8default:Short1-2

J22default:Shorted

J17default:OPEN

C82

2.2uF

C82

2.2uF

1

2

C64

.01uF

C64

.01uF

1

2

C20

.01uF

C20

.01uF

1

2

R49

33.2K

R49

33.2K

C33

10uF

10%

16V

C33

10uF

10%

16V

1

2

C37

.1uF

C37

.1uF

1

2

J14

BANANA_JACK_BLK

J14

BANANA_JACK_BLK

C67

.1uF

10%

16V

C67

.1uF

10%

16V

1

2

U9

TPS76750QPWP

U9

TPS76750QPWP

GND/HTSNK2

2

NC3

17

GND

3

NC1

4

EN

5

IN1

6

NC2

8

GND/HTSNK5

1

1

GND/HTSNK1

1

GND/HTSNK3

9

OUT1

13

GND/HTSNK4

10

IN2

7

RESET

16

GND/HTSNK6

12

OUT2

14

FB/NC

15

NC4

18

GND/HTSNK7

19

GND/HTSNK8

20

PWRP

AD

21

C89

10uF

10%

16V

C89

10uF

10%

16V

1

2

C32

.1uF

10%

16V

C32

.1uF

10%

16V

1

2

C12

.01uF

C12

.01uF

1

2

C63

.1uF

C63

.1uF

1

2

C19

.1uF

C19

.1uF

1

2

+

C101

47uF

10V

20%

+

C101

47uF

10V

20%

C84

2.2uF

C84

2.2uF

1

2

C36

.01uF

C36

.01uF

1

2

C7

.1uF

C7

.1uF

1

2

+

C102

10uF

16V

10%

LOWESR

+

C102

10uF

16V

10%

LOWESR

C35

.1uF

C35

.1uF

1

2

R59

10K

R59

10K

U1

1

TPS76733QPWP

U1

1

TPS76733QPWP

GND/HTSNK2

2

NC3

17

GND

3

NC1

4

EN

5

IN1

6

NC2

8

GND/HTSNK5

1

1

GND/HTSNK1

1

GND/HTSNK3

9

OUT1

13

GND/HTSNK4

10

IN2

7

RESET

16

GND/HTSNK6

12

OUT2

14

FB/NC

15

NC4

18

GND/HTSNK7

19

GND/HTSNK8

20

PWRP

AD

21

C8

.01uF

C8

.01uF

1

2

C62

.01uF

C62

.01uF

1

2

+

C51

47uF

10V

20%

+

C51

47uF

10V

20%

R50

30.1K

R50

30.1K

U12

TPS76701QPWP

U12

TPS76701QPWP

GND/HTSNK2

2

NC3

17

GND

3

NC1

4

EN

5

IN1

6

NC2

8

GND/HTSNK5

1

1

GND/HTSNK1

1

GND/HTSNK3

9

OUT1

13

GND/HTSNK4

10

IN2

7

RESET

16

GND/HTSNK6

12

OUT2

14

FB/NC

15

NC4

18

GND/HTSNK7

19

GND/HTSNK8

20

PWRP

AD

21

C15

.1uF

C15

.1uF

1

2

C61

.1uF

C61

.1uF

1

2

+

C96

47uF

10V

20%

+

C96

47uF

10V

20%

R45

100K

R45

100K

+

C103

10uF

16V

10%

LOWESR

+

C103

10uF

16V

10%

LOWESR

R51

100K

R51

100K

C60

.01uF

C60

.01uF

1

2

C59

.1uF

C59

.1uF

1

2

C18

.01uF

C18

.01uF

1

2

+

C108

100uF

16V

20%

+

C108

100uF

16V

20%

C55

.1uF

C55

.1uF

1

2

+

C97

47uF

10V

20%

+

C97

47uF

10V

20%

C58

.01uF

C58

.01uF

1

2

C1

1

.1uF

C1

1

.1uF

1

2

68OHM@100MHz

FB1

1

68OHM@100MHz

FB1

1

68OHM@100MHz

FB13

68OHM@100MHz

FB13

C57

.1uF

C57

.1uF

1

2

C85

.1uF

C85

.1uF

1

2

C30

.01uF

C30

.01uF

1

2

C81

.1uF

C81

.1uF

1

2

C54

10uF

10%

16V

C54

10uF

10%

16V

1

2

C41

.1uF

C41

.1uF

1

2

C56

.01uF

C56

.01uF

1

2

C14

.01uF

C14

.01uF

1

2

J17J17

1

2

C29

.1uF

C29

.1uF

1

2

C28

.01uF

C28

.01uF

1

2

C50

.01uF

C50

.01uF

1

2

D16

LEDgreen

+6V

D16

LEDgreen

+6V

C45

.1uF

C45

.1uF

1

2

68OHM@100MHz

FB12

68OHM@100MHz

FB12

C40

.01uF

C40

.01uF

1

2

C39

.1uF

C39

.1uF

1

2

C27

.1uF

C27

.1uF

1

2

J7

CONNJACKPWR

J7

CONNJACKPWR

2

3

1

C104

.1uF

10%

16V

C104

.1uF

10%

16V

1

2

C17

.1uF

C17

.1uF

1

2

R109

300

R109

300

C44

.01uF

C44

.01uF

1

2

C43

.1uF

C43

.1uF

1

2

R58

24.3K

R58

24.3K

C349

10uF

10%

16V

C349

10uF

10%

16V

1

2

+

C53

10uF

16V

10%

LOWESR

+

C53

10uF

16V

10%

LOWESR

C49

.1uF

C49

.1uF

1

2

C26

.01uF

C26

.01uF

1

2

C10

.01uF

C10

.01uF

1

2

C106

10uF

10%

16V

C106

10uF

10%

16V

1

2

C42

.01uF

C42

.01uF

1

2

+

C109

100uF

16V

20%

+

C109

100uF

16V

20%

U1-5

XC4VLX25-SF363-BGA

U1-5

XC4VLX25-SF363-BGA

VCCO_0

D10

VCCO_0

U1

1

VCCO_1

D7

VCCO_1

D14

VCCO_2

U7

VCCO_3

A9

VCCO_2

U14

VCCO_3

A12

VCCO_4

Y8

VCCO_4

Y13

VCCO_5

K15

VCCO_5

L15

VCCO_5

A17

VCCO_5

E17

VCCO_5

L18

VCCO_5

D20

VCCO_5

J20

VCCO_5

N20

VCCO_6

D1

VCCO_6

J1

VCCO_6

N1

VCCO_6

L3

VCCO_6

A4

VCCO_6

E4

VCCO_6

K6

VCCO_6

L6

VCCO_7

T16

VCCO_7

Y18

VCCO_7

U20

VCCO_8

U1

VCCO_8

Y3

VCCO_8

T5

GN

D

B1

GN

D

W1

GN

D

Y1

GN

D

Y2

GN

D

G3

GND

P3

GN

D

C7

GN

D

H7

GN

D

J7

GN

D

K7

GN

D

L7

GN

D

M7

GN

D

N7

GN

D

V7

GN

D

G8

GND

P8

GN

D

G9

GND

P9

GN

D

G1

0

GND

P10

GN

D

U1

0

GN

D

A2

GN

D

D1

1

GN

D

G1

1

GND

P11

GN

D

G1

2

GND

P12

GN

D

G1

3

GND

P13

GN

D

C1

4

GN

D

H1

4

GN

D

J1

4

GN

D

K14

GN

D

L1

4

GN

D

M1

4

GN

D

N1

4

GN

D

V14

GN

D

G1

8

GND

P18

GN

D

A19

GN

D

Y19

GN

D

A20

GN

D

B20

GN

D

W2

0

GN

D

Y20

VREFP_SM

W14

VREFN_SM

W15

A

VDD_SM

W16

VP_SM

Y14

VN_SM

Y15

A

VSS_SM

Y16

VCCAUX1

H6

VCCAUX2

N6

VCCAUX3

F8

VCCAUX4

R8

VCCAUX5

F13

VCCAUX6

R13

VCCAUX7

H15

VCCAUX8

N15

VCCINT1

G6

VCCINT2

P6

VCCINT3

F7

VCCINT4

G7

VCCINT5

P7

VCCINT6

R7

VCCINT7

F14

VCCINT8

G14

VCCINT9

P14

VCCINT10

R14

VCCINT1

1

G15

VCCINT12

P15

J22J22

1

2

R48

100K

R48

100K

+

C88

47uF

10V

20%

+

C88

47uF

10V

20%

C52

10uF

10%

16V

C52

10uF

10%

16V

1

2

C48

.01uF

C48

.01uF

1

2

C25

.1uF

C25

.1uF

1

2

U13

TPS76733QPWP

U13

TPS76733QPWP

GND/HTSNK2

2

NC3

17

GND

3

NC1

4

EN

5

IN1

6

NC2

8

GND/HTSNK5

1

1

GND/HTSNK1

1

GND/HTSNK3

9

OUT1

13

GND/HTSNK4

10

IN2

7

RESET

16

GND/HTSNK6

12

OUT2

14

FB/NC

15

NC4

18

GND/HTSNK7

19

GND/HTSNK8

20

PWRP

AD

21

U15

TPS73225-SOT23

U15

TPS73225-SOT23

EN

3

IN

1

GND

2

OUT

5

NC/FB

4

U7

TPS73018-SOT23

U7

TPS73018-SOT23

EN

3

IN

1

GND

2

OUT

5

NC/FB

4

+

C98

10uF

16V

10%

LOWESR

+

C98

10uF

16V

10%

LOWESR

68OHM@100MHz

FB16

68OHM@100MHz

FB16

C99

1uF

20%

25V

C99

1uF

20%

25V

+

C105

47uF

10V

20%

+

C105

47uF

10V

20%

J15

BANANA_JACK_RED

J15

BANANA_JACK_RED

U14

PTH03000W

U14

PTH03000W

GND

1

V

in

2

INHIBIT

3

V

o_ADJ

4

V

out

5

C47

.1uF

C47

.1uF

1

2

C24

.01uF

C24

.01uF

1

2

C13

.1uF

C13

.1uF

1

2

R13

100K

R13

100K

C34

.1uF

10%

16V

C34

.1uF

10%

16V

1

2

JP8JP8

1

3

2

C46

.01uF

C46

.01uF

1

2

C23

.1uF

C23

.1uF

1

2

68OHM@100MHz

FB10

68OHM@100MHz

FB10

C22

.01uF

C22

.01uF

1

2

C16

.01uF

C16

.01uF

1

2

C100

.1uF

10%

16V

C100

.1uF

10%

16V

1

2

C66

.01uF

C66

.01uF

1

2

C65

.1uF

C65

.1uF

1

2

C21

.1uF

C21

.1uF

1

2

C9

.1uF

C9

.1uF

1

2

C348

10uF

10%

16V

C348

10uF

10%

16V

1

2

C38

.01uF

C38

.01uF

1

2

+

C107

10uF

16V

10%

LOWESR

+

C107

10uF

16V

10%

LOWESR

C31

.01uF

C31

.01uF

www.ti.com

Schematics and Bill of Materials

Figure 13. Schematic Diagram Page 1

SLAU212A – April 2007 – Revised August 2008

TSW1200EVM: High-Speed LVDS Deserializer and Analysis System

23

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Summary of Contents for TSW1200EVM

Page 1: ...1200 User Interface Installation 13 8 Hardware Device Manager 14 9 Found New Hardware Windows 15 10 User Interface Initial Setup Screen 16 11 User Interface Single FFT format 20 12 User Interface Time...

Page 2: ...EW is a trademark of National Instruments Corporation MATLAB is a trademark of The MathWorks Inc Xilinx is a trademark of Xilinx Inc TSW1200EVM High Speed LVDS Deserializer and Analysis System 2 SLAU2...

Page 3: ...DS line one bit at a time at a higher data rate than the sample rate of the ADC The firmware in the FPGA on the TSW1200 is designed to accommodate both parallel DDR formats and serial LVDS formats alt...

Page 4: ...e ended CMOS output The TSW1200 FPGA has enough FIFO buffer to capture as much as a 65536 sample record length from the continuous sample data stream coming from the LVDS ADC interface The TSW1200 FPG...

Page 5: ...N TI recommends that the black banana jack J14 be connected to a bench ground even if the 6 V external power brick is connected to J7 Intermittent loss of the USB connection can sometimes be observed...

Page 6: ...FPGA Bit file CFG1 jumper J10 set to LO and jumper J11 set to HI is defined for use with ADC EVMs that employ a parallel LVDS DDR dual data rate format Bit file CFG2 is defined for use with ADC EVMs t...

Page 7: ...one JTAG device connected to the TDI of the next JTAG device The normal setting of the JTAG jumpers is to connect the TDI of the JTAG connector to the TDI pin of the FPGA EEPROM through jumper J12 pi...

Page 8: ...derived from the onboard oscillator LED D2 labeled DCM on the TSW1200 silkscreen which is an abbreviation for the digital clock manager block of logic in the FPGA flashes when an LVDS clock from the...

Page 9: ...amtec connector Fourteen LVDS data pairs plus two LVDS clock pairs have a defined position in the connector pinout that is common between the TSW1200EVM and many TI ADC EVMs For the parallel LVDS DDR...

Page 10: ...he operational mode of the ADC under evaluation There SPI signals are by default not connected on the ADC EVM until a 0 resistor is installed on the EVM to enable control of the SPI port from the TSW1...

Page 11: ...ure depth for an FFT on a million continuous data samples or more For this the output header posts are available so that a logic analyzer can be used to capture ADC data in real time The pinout of the...

Page 12: ...1200 Installation CD and are installed during the installation process The USB is accessed as a virtual communication port VCP and shows up in the Hardware Device Manager as TSW1200 under COM ports an...

Page 13: ...200 User Interface Installation If the TSW1200 user interface software is being installed on a machine that has an older version TI recommends that you first remove the old TSW1200 installation using...

Page 14: ...onnected the TSW1200EVM to the PC the TSW1200 can be located in the Hardware Device Manager as shown in Figure 8 The TSW1200 appears as TSW1200 as a COM port Each time the USB cable is connected it is...

Page 15: ...iguration for the PC If the Found New Hardware Wizard does appear again when the USB cable is reconnected follow the same responses to the dialog boxes as when the TSW1200 was first installed Figure 9...

Page 16: ...chosen from the test pulldown menu Figure 10 User Interface Initial Setup Screen The toolbar contains options and settings that are independent of the device selected for test or the test to be perfor...

Page 17: ...st Later revisions of the TSW1200 software will allow for setting test parameters for a Dual Tone FFT test and the ACPR test For a Single Tone FFT test the RMS line may be enabled or disabled When ena...

Page 18: ...nce statistics Time Domain displays the raw captured data in the format of a logic analyzer display and output level over time In the Window Display drop down menu the user chooses a windowing functio...

Page 19: ...marker to any place in the power spectrum such as a noise spur that is not already marked as a harmonic By default this additional marker initially goes to the highest spur that is not identified as...

Page 20: ...d third fourth and fifth harmonics of the input frequency and the user selectable marker are displayed in either dBFS or dBc Test setup Input parameters relevant to the test are repeated particularly...

Page 21: ...n results window In the upper half of the window the arithmetic value of the sample is represented on the vertical scale In the lower half of the window the individual bits of the data are displayed a...

Page 22: ...e can open a com port to the USB channel and can perform the register reads and writes to the TSW1200 hardware One common request for another user interface is MATLAB as the user might then want to us...

Page 23: ...1 2 C17 1uF C17 1uF 1 2 R109 300 R109 300 C44 01uF C44 01uF 1 2 C43 1uF C43 1uF 1 2 R58 24 3K R58 24 3K C349 10uF 10 16V C349 10uF 10 16V 1 2 C53 10uF 16V 10 LOW ESR C53 10uF 16V 10 LOW ESR C49 1uF C4...

Page 24: ...SDA 10 GND8 8 P3 3 30 P3 1 31 P3 0 32 GND28 28 X2 26 RI CP 16 DCD 15 VCC25 25 U1 4 XC4VLX25 SF363 BGA U1 4 XC4VLX25 SF363 BGA IO_L20P_7 R19 IO_L20N_VREF_7 R20 IO_L21P_7 R15 IO_L21N_7 R16 IO_L23P_VRN_7...

Page 25: ...F C79 10uF J10 HEADER 3 J10 HEADER 3 1 2 3 J2 J2 2 4 6 8 10 12 14 1 3 5 7 9 11 13 C86 1uF C86 1uF 1 2 R3 0 ohm R3 0 ohm C83 3 3uF C83 3 3uF R52 4 7K R52 4 7K R2 0 ohm R2 0 ohm R33 1K R33 1K Q3 DTC114E...

Page 26: ...6 IO_L4P_5 B17 IO_L4N_VREF_5 C17 IO_L5P_5 D16 IO_L5N_5 E16 IO_L6P_5 A18 IO_L6N_5 B18 IO_L7P_5 D17 IO_L7N_5 D18 IO_L8P_CC_LC_5 B19 IO_L8N_CC_LC_5 C20 IO_L9P_CC_LC_5 F18 IO_L9N_CC_LC_5 E18 IO_L10P_5 C18...

Page 27: ...10 8 9 J18 HDR 16X2 MALE 100CTR TI_SILKTEXT J18 HDR 16X2 MALE 100CTR TI_SILKTEXT 1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 J6 HEADER MALE 20x2 POS 100 VERT...

Page 28: ...onic 10 10V 2 C77 C78 22 pF 603 GRM1885C2A220JA01D Murata 5 100V 2 C81 C85 0 1 F 603 ECJ 1VB1H104K Panasonic 10 50V 2 C82 C84 2 2 F 603 ECJ 1VB1A225K Panasonic 10 10V 1 C83 3 3 F TANT_B TAJB335K016R A...

Page 29: ...o 1 1 10W 8 R27 R30 22 603 RC0603FR 0722RL Yageo 1 1 10W R60 R63 6 R33 R34 R37 R 1K 603 ERJ 3EKF1001V Panasonic 1 1 10W 38 R46 R47 2 R35 R36 100 603 ERJ 3EKF1000V Panasonic 1 1 10W 1 R45 100K 603 ERJ...

Page 30: ...I Provide pad 1 U14 PTH03000W SMD_PWRMOD_EUT5 PTH03000WAS TI TI Provide 1 U15 TPS73225 SOT23 DBV5 TPS73225DBVT TI TI Provide 1 Y1 12MHz w 18pF smd_xtal_AMB3B ABM3B 12 000MHZ 10 1 Abracon U T 4 Screw 4...

Page 31: ...m Circuit Board Layout and Layer Stackup Figure 19 TSW1200C Layout Layer Two SLAU212A April 2007 Revised August 2008 TSW1200EVM High Speed LVDS Deserializer and Analysis System 31 Submit Documentation...

Page 32: ...ard Layout and Layer Stackup www ti com Figure 20 TSW1200C Layout Power Plane 32 TSW1200EVM High Speed LVDS Deserializer and Analysis System SLAU212A April 2007 Revised August 2008 Submit Documentatio...

Page 33: ...Circuit Board Layout and Layer Stackup Figure 21 TSW1200C Layout Ground Plane SLAU212A April 2007 Revised August 2008 TSW1200EVM High Speed LVDS Deserializer and Analysis System 33 Submit Documentatio...

Page 34: ...Board Layout and Layer Stackup www ti com Figure 22 TSW1200C Layout Layer 5 34 TSW1200EVM High Speed LVDS Deserializer and Analysis System SLAU212A April 2007 Revised August 2008 Submit Documentation...

Page 35: ...i com Circuit Board Layout and Layer Stackup Figure 23 TSW1200C Layer 6 SLAU212A April 2007 Revised August 2008 TSW1200EVM High Speed LVDS Deserializer and Analysis System 35 Submit Documentation Feed...

Page 36: ...Board Layout and Layer Stackup www ti com Figure 24 TSW1200C Bottom Layer 36 TSW1200EVM High Speed LVDS Deserializer and Analysis System SLAU212A April 2007 Revised August 2008 Submit Documentation F...

Page 37: ...com Circuit Board Layout and Layer Stackup Figure 25 Circuit Board Stackup SLAU212A April 2007 Revised August 2008 TSW1200EVM High Speed LVDS Deserializer and Analysis System 37 Submit Documentation F...

Page 38: ...uct This notice contains important safety information about temperatures and voltages For additional information on TI s environmental and or safety programs please contact the TI application engineer...

Page 39: ...siness practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product wo...

Page 40: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Texas Instruments TSW1200EVM...

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