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477

Introduction

This report describes special features of the digital I/O port control registers (address range 1020h to
102Fh), not fully documented in the TMS370 Family User’s Guide.

These features should be taken into account when memory expansion is used in microcomputer mode to
prevent any uncontrolled effect.

Special Features

In microcomputer mode, with bus expansion (function A or B) and internal program memory disabled,
the internal program memory locations and 1020h to 102Fh are decoded as external addresses.

Memory accesses to the locations 1020h to 102Fh have following effect:

•

Writes are executed externally as expected, but also internally (not expected). In other words,
the internal I/O configuration register using the same address is also modified. This may corrupt
the port pins initially set as alternate function A or B, if port control registers (XPORT2 and/or
DPORT1) have changed. It may also affect those port pins which were originally configured as
general purpose I/Os.

•

Reads are only performed from the external data bus as expected

.

To prevent corrupting the bus expansion mode:

•

The addresses of XPORT2 and DPORT1 should not be used as external.

•

Addresses used to control general purpose I/Os should not be used as external addresses.

•

Use of read-modify instructions at 102Xh locations is not available since it would read external
data and write or modify the internal I/O configuration registers located at the same addresses.

The table below summarizes read and write functions at the locations 1020h to 102Fh in all the operating
modes.

Table 1. Read and Write Functions

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁ

Microcomputer

Mode

ÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁ

Microprocessor

Mode

Á

Á

Á

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

Internal Memory

Enabled

ÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁ

Internal Write & Read

ÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁ

Internal Write & Read

(Internal Write has no effect on I/O’s)

Á

Á

ÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁ

Á

Á

ÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁ

Internal Memory

Disabled

ÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁ

Á

Á

ÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁ

External Write & Read

Internal Write

(Internal write may affect I/O’s)

ÁÁÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁ

Á

Á

ÁÁÁÁÁÁÁÁÁ

Á

ÁÁÁÁÁÁÁÁÁÁÁ

External Write & Read

Internal Write

(Internal write has no effect on I/O’s)

Á

Á

Á

Á

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁ

Á

Á

*

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Summary of Contents for TMS370 Series

Page 1: ...TMS370 Microcontroller Family Application Book 1996 8 Bit Microcontroller Family ...

Page 2: ...Printed in U S A February 1996 SPNA017 ...

Page 3: ...1996 Application TMS370 Microcontroller Family Book ...

Page 4: ...TMS370 Microcontroller Family Application Book Microcontroller Products Semiconductor Group SPNA017 February 1996 ...

Page 5: ...NED INTENDED AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE SUPPORT APPLICATIONS DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS Inclusion of TI products in such applications is understood to be fully at the risk of the customer Use of TI products in such applications requires the written approval of an appropriate TI officer Questions concerning potential risk applications should be dir...

Page 6: ... Number Comparison 37 Floating Point Division 39 Floating Point Multiplication 43 Floating Point Increment Decrement 46 Floating Point Number Test 49 Floating Point Number Negation 50 Floating Point To Signed 8 Bit Integer Conversion 51 Floating Point To Signed Long 16 Bit Integer Conversion 53 Floating Point To Unsigned 8 Bit Integer Conversion 55 Floating Point To Unsigned Long 16 Bit Integer Co...

Page 7: ...des 111 TheMasterMode 111 TheSlaveMode 111 Configuring the SPI 112 SPIDataFormat TransmittingandReceiving 112 TheSPICLKandDataTransferRate 113 Controlling the SPI through Interrupts and Flag Checking 114 The TALK Bit and Multiprocessor Communications 115 Considerations When Using the SPI 115 Data Integrity and the SPI 116 SPI Module Software Examples 117 Common Equates 117 Master SPI Configuration...

Page 8: ...ltiprocessing Control 155 Routine 155 System Controller Configuration 156 Routine 156 Nine Bit Data Protocol 157 Routine 157 HALT Mode Wakeup Using the SCI Receiver 158 Routine 158 SCI Module Specific Applications 159 RS 232 C Interface 159 Interface TMS370C050 to RSĆ232ĆC Connection 159 SCI Module Specific Applications 160 Routine 161 Dumb Terminal Driver 164 Use TMS370C050 SCI to Interface to Du...

Page 9: ...Examples 220 Real Time System Control Periodic Interrupt of T1 221 Output Pulse Width Generation 1 kHz Square Wave 223 Pulse Width Modulation 1 225 Pulse Width Modulation 2 227 Pulse Position Modulation PPM 229 Pulse Width Measurement Using Pulse Accumulation Clock Source 231 Counting External Pulses Relative to an External Signal 233 Output Pulse Drive Referenced to Input Signal TRIAC Controller ...

Page 10: ...al Module Using the TMS370 ADC1 Module 311 Introduction 313 Module Description 313 Principles of Operation 315 Functional Description 316 Design Considerations 316 A D Input Pin Model 316 Analog Input Pin Connection 317 Analog Input Conditioning 319 Resolution 322 Ratiometric Conversion 324 Sampling Frequency 324 Analog Reference and Layout Considerations 325 Software Routines 328 Common Equates 3...

Page 11: ...duction 387 Register Equates 387 Using The Hardware Default Timer 388 Square Wave PWM On OP1 388 1 5 1 1 1 5 1 PWM With Period and Duty Cycle Change 391 PACT Peripheral Initialization 391 PACT Command Definition Initialization 391 Virtual Timer PWM 394 2 0 1 2 1 4 2 0 1 2 1 4 Synchronized Pulses On External Event 403 1 3 1 1 1 3 1 Pulse Width Measurement PWM 413 0 1 7 1 12 01 0 0 2 2 01 0 Using PA...

Page 12: ...pansion Examples Using Memory Expansion in Microcomputer Mode With Internal Memory Disabled 475 Introduction 477 Special Features 477 Interfacing and Accessing External Memory 479 Microcomputer Interface Example 481 Read Cycle Timing 484 V alid AddressĆtoĆData Read Time Requirement 484 ChipĆSelect LowĆtoĆData Read Requirements 485 ChipĆSelect HighĆtoĆNext Data Bus Drive Requirements 486 Read Data ...

Page 13: ...res 514 Minimize Routing Distances 514 Short Routes for HighĆfrequency Signals 514 Grounding 514 Digital Grid the Ground 515 Analog Ground 518 Noisy Ground 518 Low Impedance Ground Node 519 Ground Width 519 Connector Grounds 519 Power Routing 519 Clock Lines 520 MultiĆlayer Boards 520 Bypassing 522 Power Bypassing VCC VSS VCC3 VSS3 522 Signal Bypassing 522 Connector Bypassing 522 Summary 523 Prior...

Page 14: ...ernal Diode Protection Circuitry 535 Designing Input Protection Circuitry for TMS370 Microcontrollers 537 Calculation of External Current Limiting Resistor Value Example 539 Cost Analysis 542 Conclusion 545 References 546 ...

Page 15: ...615 37 065 5 3 0 5 6064 0 0 3 30 5 0 6 4 0 3 5 3 03 54 4 30 064 0 6 5 0 03 5 404 30 064 0 6 5 0 03 5 7 3 1 3 5 0 08 35 3 4 55 3 1 3 5 0 08 35 5 3 3 5 3 9 1 05 5 26 4 5 0 9 1 0 3 65 Automatic Baud Rate Calculation 193 5 3 9 1 650 6 7 03 Using the TMS370 Timer Modules 201 3 0 3 3 4 3 0 063 5 30 3 3 63104 5 0 06 5 3 0 3 4 4 95 3 5 33615 6 0 1 3 0 03 1563 0 1 3 0 03 5 30 3 3 63104 6 0 1 3 0 03 6 1563 ...

Page 16: ... 3 1 3 9 1 0 5 3 3 6 550 3 4 40 65 0 50 54 3 4 3 3 5 3 45 40 5 5 3 3 6 5 5 0 4 505 165 0 3 0 80 5 1 6 3 0 7 34 0 4 64 26 5 1 5 3 6 58 5 0 0 1 35 5 3 6 5 5 0 0 0 1 35 5 3 0 5 063 1 0 5 3 0 7 34 0 03 6 1 3 563 403 5 3 6503 3 6 5 3 5 3 3 6 5 4 5 3 3 6 5 4 0 58 3 065 0 530 45 3 03 1 3 4 3 3 5 3 45 4 6 5 0 0 3 0 5 3 5 0 7 34 0 3 6 5 0 0 3 4 0 7 35 3 4 6 5 0 0 3 4 0 7 35 3 4 0 3 0 45 5 1 0 5 463 5 0 4 7...

Page 17: ...own Resistor 447 Interfacing and Accessing External Memory 479 1 Microcomputer Interface Example 482 2 V alid AddressĆtoĆData Read Timing 485 3 ChipĆSelect LowĆtoĆData Read Timing 486 4 ChipĆSelect HighĆtoĆNext Data Bus Drive Timing 486 5 Read Data Hold After ChipĆSelect High Timing 487 6 Write Data SetĆUp Timing 488 7 Write Data Hold After ChipĆSelect High 489 8 Peripheral File Frame 2 Digital Po...

Page 18: ...tions for TMS370 Family Microcontroller Devices 5 Binary to BCD Conversion on the TMS370 21 1 Register Values 23 BCD String Addition With the TMS370 25 1 Register Values and Functions 27 RAM Self Test Routine 67 1 Register Values 69 ROM Checksum on the TMS370 71 1 Register and Function Values 73 Table Search With the TMS370 75 1 Register and Expression Functions 77 Bubble Sort With the TMS370 79 1...

Page 19: ...dule 311 1 Key OpĆAmp Parameters 319 2 Analog Input Table 331 3 Amplifier Gain Factor 339 4 Test Conditions 362 Using Memory Expansion in Microcomputer Mode With Internal Memory Disabled 475 1 Read and Write Functions 477 2 WaitĆState Control Bits 483 3 Memory Interface Timing 483 4 Port Configuration Registers SetĆUp 492 Cost Effective Input Protection Circuitry for the Texas Instruments TMS370 F...

Page 20: ...1 Part I Introduction ...

Page 21: ...2 ...

Page 22: ...3 Introduction Microcontroller Products Semiconductor Group Texas Instruments ...

Page 23: ...4 ...

Page 24: ... Fax 713 274 4203 Other info including routines will also be available on TI s world wide web site http www ti com Typical Applications In expanding its powerful TMS370 family of microcontrollers TI offers many configurable devices for specific applications As microcontrollers have evolved TI has added multiple peripheral functions to chips that originally had only a CPU memory and I O blocks Now ...

Page 25: ...6 ...

Page 26: ...7 Part II Software Routines Part II contains three sections Arithmetic 7 Memory Operations 61 Specific Functionality 83 ...

Page 27: ...8 ...

Page 28: ...9 16 16 32 Bit Multiplication With the TMS370 Microcontroller Products Semiconductor Group Texas Instruments ...

Page 29: ...10 ...

Page 30: ... EQU R6 MSbyte of the final result RSLT2 EQU R7 RSLT1 EQU R8 RSLT0 EQU R9 LSbyte of the final result MPY32 CLR RSLT2 Clear the present value CLR RSLT3 MPY XL YL Multiply LSbytes MOVW B RSLT0 Store in result register 0 MPY XH YL Get XHYL ADD R1 RSLT1 Add to existing result XLYL ADC R0 RSLT2 Add carry if present ADC 0 RSLT3 Add if carry present MPY XL YH Multiply to get XLYH ADD R1 RSLT1 Add to exis...

Page 31: ...12 ...

Page 32: ...13 Binary Division With the TMS370 Microcontroller Products Semiconductor Group Texas Instruments ...

Page 33: ...14 ...

Page 34: ...vidend Divisor R2 Routine TEXT 7000h FLAGS EQU R7 Register location of FLAG bits OVERFLOW DBIT 0 FLAGS Bit 0 of FLAGS register is OVERFLOW bit Register assignments R1 R2 contain the dividend MSbyte LSbyte R3 contains the divisor R4 R5 contain the quotient MSbyte LSbyte after operation Register B holds the remainder after operation DIVIDE8 CLR A Clear MSbyte of registers A B DIV R3 A Divide dividen...

Page 35: ...ter operation Registers A and B hold the remainder after operation DIV16 MOV 16 R6 Set loop counter to 16 one for each quotient bit CLR A Initialize result register MSbyte CLR B Initialize result register LSbyte DIVLOP RLC R3 Multiply dividend by 2 MSbyte RLC R2 RLC B Shift dividend into A B for comparison RLC A to divisor JNC SKIP1 Check for possible error condition that SUB R5 B results when a 1...

Page 36: ...17 BCD to Binary Conversion on the TMS370 Microcontroller Products Semiconductor Group Texas Instruments ...

Page 37: ...18 ...

Page 38: ...s may seem complex but it works quickly and uses few bytes Routine TEXT 7000h BH EQU R2 Binary number MSbyte BL EQU R3 Binary number LSbyte DH EQU R4 Decimal number MSbyte DL EQU R5 Decimal number LSbyte D0 ones D1 tens D2 hundreds D3 thousands TOP CLR BH Clear out binary MSbyte MOV DL BL D0 to B0 AND 0Fh BL Convert D0 MOV DL A D1 10 D1 8 D1 2 AND 0F0h A Isolate D1 MOV A B B D1 16 SWAP R1 B D1 RR ...

Page 39: ...20 ...

Page 40: ...21 Binary to BCD Conversion on the TMS370 Microcontroller Products Semiconductor Group Texas Instruments ...

Page 41: ...22 ...

Page 42: ...RY LSbyte ZERO R5 XX ZERO Routine TEXT 7000H Absolute start address BN2BCD CLR A Prepare answer registers CLR B CLR R2 MOV 16 R5 Move loop count to register LOOP RLC R4 Shift higher binary bit out RLC R3 Carry contains higher bit DAC R2 R2 Double the number then add the binary bit DAC R1 B Binary bit a 1 in carry on the 1st time is DAC R0 A doubled 16 times DJNZ R5 LOOP Do this 16 times once for e...

Page 43: ...24 ...

Page 44: ...25 BCD String Addition With the TMS370 Microcontroller Products Semiconductor Group Texas Instruments ...

Page 45: ...26 ...

Page 46: ...orary save register STR1 BINARY MSbyte no change BCD string STR2 BINARY LSbyte STR1 STR2 Target string 6 bytes max Routine Decimal addition subroutine Stack must have 3 available bytes On output STR2 STR1 STR2 TEXT 7000h Absolute start address STR1 EQU 80E0h Start of first string STR2 EQU 80F0h Start of second string and result ADDBCD CLRC Clear carry bit PUSH ST Save status to stack LOOP MOV STR1...

Page 47: ...28 ...

Page 48: ...29 TMS370 Floating Point Package Microcontroller Products Semiconductor Group Texas Instruments ...

Page 49: ...30 ...

Page 50: ...nt number comparison Floating point division Floating point multiplication Floating point increment decrement Floating point number test Floating point negation Floating point to signed 8 bit integer conversion Floating point to signed long 16 bit integer conversion Floating point to unsigned 8 bit integer conversion Floating point to unsigned long 16 bit integer conversion Signed 8 bit integer to...

Page 51: ...27 exp 80h real exp 80h 128 0 The mantissa contains 15 bits plus an implied bit The layout is m0 m1 m2 m15 The m0 bit is implied and is always 1 The value of each mi is the reciprocal of 2 to the ith power So the layout in terms of values is 1 1 2 1 4 1 8 1 16 1 32 1 64 1 128 1 256 1 512 1 1024 1 2048 Given the above format some special floating point values are ZERO 000000h 2 128 approx 2 94E 39 ...

Page 52: ...s OP1 OP2 Registers used Register Before After Status XX Modified R14 OP1 exponent Modified R15 OP1 mantissa MSB Modified R16 OP1 mantissa LSB Modified R17 OP2 exponent Result exponent R18 OP2 mantissa MSB Result mantissa MSB R19 OP2 mantissa LSB Result mantissa LSB Size 200 Bytes Stack space 4 Bytes Notes 1 Some special considerations for floating point operations are ZERO OP2 OP2 OP1 ZERO OP1 ZE...

Page 53: ...sub fp_sub cmpbit sign2 Enter subtraction here fp_add btjo 0ffh exp2 chk_op1 Check for adding zero as OP2 btjo 07fh msb2 chk_op1 btjo 0ffh lsb2 chk_op1 op2zero mov exp1 exp2 OP2 zero so result will be OP1 movw lsb1 lsb2 rts chk_op1 btjo 0ffh exp1 calc Check for subtracting zero btjo 0ffh msb1 calc btjo 0ffh lsb1 calc byebye rts calc push b mov exp2 b Find the difference between sub exp1 b exponent...

Page 54: ...rc lsb2 inc exp2 jz maxval If overflow occurs return max value done and 7fh msb2 Clear the implied one bit and 080h a Clear the subtract flag or a msb2 Set sign bit if appropriate pop a done2 pop b rts sub sub lsb1 lsb2 sbb msb1 msb2 jc skp2 If borrow occurred exp1 exp2 man1 man2 xor 80h a toggle the sign bit and complement result inv msb2 compl lsb2 adc 0 msb2 skp2 jn done Adjust the mantissa if ...

Page 55: ...36 maxval mov 0ffh exp2 Create maximum value movw 07fffh lsb2 or a msb2 Set sign bit as appropriate pop a pop b rts ...

Page 56: ...t on result R14 OP1 exponent OP1 exponent R15 OP1 mantissa MSB OP1 mantissa MSB R16 OP1 mantissa LSB OP1 mantissa LSB R17 OP2 exponent OP2 exponent R18 OP2 mantissa MSB Modified R19 OP2 mantissa LSB OP2 mantissa LSB The status register will be set according to the result of the compare C 0 V 0 Z 1 if OP1 is bit for bit the same as OP2 0 otherwise N 0 if OP2 is greater than or equal to OP1 1 otherw...

Page 57: ...n Test JN NEG MSB2 to check sign Make appropriate dummy move to set JMP NONEG status RTS SAMESIGN POP msb2 Restore MSB2 CMP exp1 exp2 OP1 OP2 JLO LESS JNE GREATER CMP msb1 msb2 JLO LESS JNE GREATER CMP lsb1 lsb2 JLO LESS JEQ DONE GREATER BTJZ 080h msb1 NONEG ABS OP2 ABS OP1 NEG MOV 080h msb2 DONE RTS LESS BTJZ 80H msb1 NEG ABS OP2 ABS OP1 NONEG MOV 01H msb2 RTS ...

Page 58: ...ting point numbers OP1 OP2 Registers used Register Before After Status XX Modified R14 OP1 exponent Modified R15 OP1 mantissa MSB Modified R16 OP1 mantissa LSB Modified R17 OP2 exponent Result exponent R18 OP2 mantissa MSB Result mantissa MSB R19 OP2 mantissa LSB Result mantissa LSB Size 189 bytes ...

Page 59: ...qu R16 EXP2 equ R17 MAN2MSB equ R18 MAN2LSB equ R19 COUNTER equ R20 FLAGS equ R23 OVFL dbit 0 FLAGS SIGN_OP1 dbit 7 MAN1MSB global fp_div fp_div PUSH A Save registers CHK_OP1 Check for OP1 ZERO MOV MAN1MSB A Use FLAGS here as dummy register OR EXP1 A OR all parts operand together OR MAN1LSB A If ZERO no bits will be ones JNZ CHK_OP2 CLR MAN2LSB OP1 is ZERO so clear OP2 as answer CLR MAN2MSB Store ...

Page 60: ...sult of division is underflow CLR MAN2LSB Store results in OP2 registers CLR MAN2MSB CLR EXP2 POP FLAGS Restore registers to original values POP COUNTER POP B POP A RTS Exit fp_div CHK_OVER Subtraction of exponents may have BTJO 0FFh EXP2 OVERFLOW overflowed If exponent is not 00 SBIT1 OVFL then result has definitely overflowed If result may be ok set flag SETUP MOV 16 COUNTER Set loop counter to ...

Page 61: ...GS Restore registers to original values POP COUNTER POP B POP A RTS Exit fp_div DIVIDE 16 x 16 division routine RLC B Multiply divend by 2 RLC A LAST1 RLC MAN1LSB Shift dividend into MAN1MSB MAN1LSB RLC MAN1MSB for comparison to divisor JNC SKIP1 Check for possible error condition SUB MAN2LSB MAN1LSB that results when a 1 is shifted past the MSB SBB MAN2MSB MAN1MSB Correct by subtracting SETC divi...

Page 62: ...lication are ZERO OP2 ZERO OP1 ZERO ZERO 2 If a multiplication results in a product which is greater than MAX_POS then it is overflow The result placed in registers R17 R18 R19 will be MAX_POS 3 If a multiplication results in a product which is less than MAX_NEG then it is overflow The result placed in registers R17 R18 R19 will be MAX_NEG 4 If a multiplication results in a product with a magnitud...

Page 63: ...n bit position OR 080h MAN2MSB ADDEXP CLR R0 Clear A for result of exponent math ADD EXP1 EXP2 Add exponents ADC 0h A Save status of carry bit from ADD SUB 080h EXP2 Correct for 128 offset ADC 0FFh A Save status of carry bit and subtract 1 from SUB JZ MULTIPLY Jump according to result of exponent math JN CHK_UNDER FF underflow 00 ok 01 definite overflow OVERFLOW Result of multiplication is overflo...

Page 64: ...R1 MAN2LSB ADC R0 MAN1LSB POP R1 Restore value of B register DONE_MULT JBIT0 IMPLIED_ONE JUSTIFY If result has no implied one need to justify result BTJZ 0FFh EXP2 INCEXP If exponent is not FFh then increment will not cause JMP OVERFLOW overflow JUSTIFY JBIT1 UNDER_BIT UNDERFLOW Previous underflow will not be corrected so result is underflow RL RSLT1 Justify result to add implied one RLC MAN2LSB R...

Page 65: ...crementing or decrementing a number with an exponent greater than or equal to 90 will have no effect 2 Incrementing or decrementing a number with an exponent less than or equal to 71 will have no effect msb2 equ r15 lsb2 equ r16 exp1 equ r17 msb1 equ r18 lsb1 equ r19 sign dbit 7 r0 Flag to indicate whether to add or subtract numbers as a result of math decflag dbit 0 r0 1 increment 0 decrement glo...

Page 66: ...If exp1 80h then OP1 1 0 adjust OP2 compl b Take absolute value of exponent diff mov 80h exp1 Set the exponent loop clrc rrc msb1 Adjust OP1 so that it has the same rrc lsb1 exponent as OP2 This is necessary djnz b loop for the two numbers to be added btjo 80h a subt Choose whether you need to add or subtract numbers based on sign of numbers and whether you are incrementing or decrementing add 80h...

Page 67: ...jmp calc needed and start with LSB msb_only inc b Adjust to 1 needs less than 7 shifts setc so only the MSB will be affected 3 rrc msb2 djnz b 3 calc btjo 80h a subtr If the sign flag is negative operands actually need to be subtracted add lsb2 lsb1 Sign flag is positive so add OP1 1 0 adc msb2 msb1 chkadj jnc done2 If carry occurs need to roll back rrc msb1 mantissa and increment exponent rrc lsb...

Page 68: ... of the status bits C N Z and V C 0 V 0 N sign bit of the floating point number Z 1 if the floating point number is ZERO 0 otherwise 2 This routine is the same as a call to fp_cmp with OP1 ZERO and OP2 the number to test exp1 equ r17 msb1 equ r18 lsb1 equ r19 global fp_tst fp_tst mov msb1 msb1 Test the MSB If negative return jn done and status register will be set correctly btjo 0ffh exp1 1 Check ...

Page 69: ...nent R18 OP1 mantissa MSB Result mantissa MSB R19 OP1 mantissa LSB Result mantissa LSB Size 17 Bytes Stack space None Notes Some special considerations for floating point negation are ZERO ZERO exp equ r17 msb equ r18 lsb equ r19 global fp_neg fp_neg text 7000h btjo 0ffh exp negate Check for zero btjo 0ffh msb negate btjo 0ffh lsb negate zero rts Number was zero return negate xor 80h msb Toggle si...

Page 70: ...verted to 0 expon equ r17 fsign dbit 7 r18 global fp_ftoi text 7000h fp_ftoi Floating point to integer conversion btjo 80h expon 1 If exponent 1 then number is too small clr a Set result 0 and return rts 1 cmp 87h expon Check for too big 127 jhs big mov r18 a Put MSB into A reg to be adjusted or 80h a Set the implied one push expon Save true value of exponent sub 87h expon Exponent 87h of shifts n...

Page 71: ...52 bigminus Number is too small to be represented as a mov 80h a signed integer Set result to max negative rts value ...

Page 72: ...nnot be represented by the signed long int the behavior is undefined 3 A float value of ZERO will be converted to 0 expon equ r17 fsign dbit 7 r18 global fp_ftol text 7000h fp_ftol Floating point to long integer conversion btjo 80h expon 1 If exponent 1 then number is too small clr a Set result 0 and return clr b rts 1 cmp 8fh expon Check for too big 32767 jhs big mov r19 b mov r18 a or 80h a Set ...

Page 73: ...minus mov 0ffh b Number is too big to be represented as a signed integer mov 7fh a Set result to max positive value rts bigminus mov 0 b Number is too small to be represented as a mov 80h a signed integer Set result to max negative rts value ...

Page 74: ... by the unsigned int the behavior is undefined 3 A float value of ZERO will be converted to 0 expon equ r17 fsign dbit 7 r18 global fp_ftou text 7000h fp_ftou Floating point to unsigned integer conversion btjo 80h expon 1 If exponent 1 then number is too small clr a Set result 0 and return rts 1 cmp 88h expon Check for too big 255 jhs big mov r18 a or 80h a Set the implied one push expon Save true...

Page 75: ...by the unsinged signed long int the behavior is undefined 3 A float value of ZERO will be converted to 0 expon equ r17 fsign dbit 7 r18 global fp_ftoul text 7000h fp_ftoul Floating point to unsigned long integer btjo 80h expon 1 If exponent 1 then number is too small clr a Set result 0 and return clr b rts 1 cmp 90h expon Check for too big 65535 jhs big mov r19 b mov r18 a or 80h a Set the implied...

Page 76: ...7 isign dbit 7 r0 fsign dbit 7 r18 global fp_itof text 7000h fp_itof Integer to floating point conversion clr r18 Initialize fp to zero clr r19 mov 87h expon Initialize exponent for 7 binary digit number btjo 0ffh a nonzero Check to make sure the number to be converted is not zero before we go any further zero clr expon Set result to fp zero rts nonzero jp pos Test for negative integer sbit1 fsign...

Page 77: ... isign dbit 7 r0 fsign dbit 7 r18 global fp_ltof text 7000h fp_ltof Long integer to floating point conversion clr r18 mov 8fh expon Set resulting exponent btjo 0ffh a nonzero Test if MSB 0 zero btjo 0ffh b pos Test if LSB 0 Since MSB 0 value must be positive if not zero clr expon Long integer is zero Return fp zero clr r19 rts nonzero jp pos Test for negative integer sbit1 fsign Integer is negativ...

Page 78: ...e Note A zero long integer value will convert to the floating point ZERO value expon equ r17 global fp_ultof text 7000h fp_ultof Unsigned long integer to floating point mov 08fh expon Set exponent of result btjo 0ffh a nonzero Test if MSB 0 zero btjo 0ffh b pos Test if LSB 0 clr expon Number is zero Set result to fp zero clr r18 clr r19 rts nonzero jn ok If MSB already has implied one then done po...

Page 79: ...mantissa LSB Size 26 Bytes Stack space None Note A zero integer value will convert to the floating point ZERO value expon equ r17 global fp_utof text 7000h fp_utof Unsigned integer to floating point conversion clr r19 Initialize MSB mov 87h expon Initialize the exponent btjo 0ffh a nonzero Test to see if integer is zero zero clr r18 Integer is zero result will be fp zero clr expon rts nonzero jn o...

Page 80: ...61 Part II Software Routines Part II contains three sections Arithmetic 7 Memory Operations 61 Specific Functionality 83 ...

Page 81: ...62 ...

Page 82: ...63 Clear RAM Microcontroller Products Semiconductor Group Texas Instruments ...

Page 83: ...64 ...

Page 84: ... B have the following functions in this routine Register A holds the initialization value Register B serves as the index into the RAM Routine TEXT 7000h Absolute start address CLEAR MOV 254 B Number of registers to clear less 2 CLR A Load the initialization value of zero LOOP MOV A 1 B Clear the location indexed by B 1 DJNZ B LOOP Loop until all RAM is cleared A and B end up as zeros ...

Page 85: ...66 ...

Page 86: ...67 RAM Self Test on the TMS370 Microcontroller Products Semiconductor Group Texas Instruments ...

Page 87: ...68 ...

Page 88: ... in FLAG 1 if error was found Routine TEXT 7000H Absolute start address FLAG EQU R2 Error register MOV 55h A Start RAM fill with 55h FILLR MOV 0FDh B Set RAM start address 3 don t change registers A B or R2 FILL1 MOV A 2 B Fill RAM with AA to 55 pattern RR A Change to beginning number DJNZ B FILL1 Fill entire RAM with pattern RR A Change to beginning number MOV 0FDh B Refresh index COMPAR CMP 2 B ...

Page 89: ...70 ...

Page 90: ...71 ROM Checksum on the TMS370 Microcontroller Products Semiconductor Group Texas Instruments ...

Page 91: ...72 ...

Page 92: ...nd a bit is set in a register The error flag bit should be cleared before the start of the routine This routine can easily be modified for other ROM sizes NOTE Addresses7FE0h through 7FEBh are reserved for TI use only and should not be used in a checksum calculation Table 1 Register and Function Values Register Before After No Error After Error A XX X X B XX X X R2 XX CHKSUM MSbyte CHKSUM MSbyte R...

Page 93: ...1 MOVW 0 R3 Reset summing register ADDLOP MOV R5 A Get ROM byte ADD A R3 Add to 16 bit sum ADC 0 R2 Add any carry INCW 1 R5 Decrement address INCW 1 R7 Decrement byte counter JC ADDLOP Continue until byte count goes past 0 MOV 7000h A Compare MSbyte stored to MSbyte sum CMP A R2 JNE ERROR Set error bit if different MOV 7001h A Compare LSbyte stored to LSbyte sum CMP A R3 JEQ EXIT Set error bit if ...

Page 94: ...75 Table Search With the TMS370 Microcontroller Products Semiconductor Group Texas Instruments ...

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Page 96: ...nction A XX B XX R2 XX Table length TABLE XX no change Long string in table STRING XX no change Target string 6 bytes max Routine TEXT 7000h Absolute start address TABLE EQU 2000h Start of data table in external RAM STRING EQU R10 Start of target string 6 bytes max SEARCH MOV 150 R2 Table length 150 bytes LOOP1 MOV 6 B String length 6 bytes LOOP2 XCHB R2 Swap pointers long string in B DEC B Reduce...

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Page 98: ...79 Bubble Sort With the TMS370 Microcontroller Products Semiconductor Group Texas Instruments ...

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Page 100: ... EQU R2 Swap has been made flag SORT CLR FLAG Reset swap flag MOV 0FFh B Load table offset value LOOP1 MOV TABLE B A Look at entry in table CMP TABLE 1 B A Look at next lower byte JHS LOOP2 If higher or equal skip to next value INC FLAG Entry is not lower set swap flag PUSH A Store upper byte MOV TABLE 1 B A Take lower byte MOV A TABLE B Put where upper was POP A Get the old upper byte MOV A TABLE...

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Page 102: ...83 Part II Software Routines Part II contains three sections Arithmetic 7 Memory Operations 61 Specific Functionality 83 ...

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Page 104: ...85 Routine to Read a 16 Key Keyboard Microcontroller Products Semiconductor Group Texas Instruments ...

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Page 106: ...1 D2 D3 D4 D5 D6 D7 TMS370 0 4 8 C 1 5 9 D 2 6 A E 3 7 B F Keys Table 1 Register Properties After After C Register Before NOKEY NEWKEY Functions Comments A dc 0 Column Temporary B dc 0 Row Temporary R2 dc 16 Key number Temporary storage for key value R3 Old key value 0FFh Key number Contains key pressed R4 Debounced 0 0 Debounce counter old key or new R5 General bits xxxxxxx0 xxxxxxx1 One bit of r...

Page 107: ...w AND 0Fh A Isolate column data JZ LOOP If no keys found check next row KEYLSB DEC R2 Decrement column offset RRC A Find column JNC KEYLSB If not column then try again NEWKEY CMP R2 R3 Is the new key the same as the old key JEQ DEBONS If it is then debounce it MOV R2 R3 Brand new key move it to current key value MOV 07 R4 Set up debounce count debounce 7 times DEBONS CMP 2 R4 Is the debounce count...

Page 108: ...89 DTMF Generation With the TMS370 Microcontroller Products Semiconductor Group Texas Instruments ...

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Page 110: ...TO THE MIDPOINT VOLTAGE DONE AUTOMATICALLY AFTER CALL DTMF CALLDTMF GENERATE DTMF DIGIT IN TONE 0 3 GENERATE TONE FOR DURATION IN TIMER TIMER 1 START AT D A MIDPOINT ON EXIT SET D A TO MIDPOINT TONE 0 3 DTMF HZ 0 941 1336 1 697 1209 2 697 1336 3 697 1477 4 770 1209 5 770 1336 6 770 1477 7 852 1209 8 852 1336 9 852 1477 A 697 1633 B 770 1633 C 852 1633 D 941 1633 E 941 1209 F 941 1477 TONE EQU R020...

Page 111: ... 697 HZ L2 EQU 004EEh 770 HZ L3 EQU 00574h 852 HZ L4 EQU 00606h 941 HZ H1 EQU 007BDh 1209 HZ H2 EQU 0088Eh 1336 HZ H3 EQU 00975h 1477 HZ H4 EQU 00A74h 1633 HZ SECT S1 0F806h DTMF EQU MOV 00Fh BDR LOWER NIBBLE OF BPORT IS OUTPUT INITIALIZE DTMF POINTERS MOV TONE B LOAD DIGIT INTO AND 00Fh B LOWER 4 BITS OF B RL B MAKE RL B ADDRESS MOV DIGIT B A LOAD MOV A CNT1 COUNT1 MOV DIGIT 1 B A LOAD MOV A ADJ1...

Page 112: ...9 AND 03Fh PRT1 1 6 BIT ADDRESS 8 MOV PRT1 1 A 9 MOV A B 9 DTMF FREQUENCY 2 ADD ADJ2 PRT2 2 ADD ADJUSTMENT 9 ADC CNT2 PRT2 1 ADD COUNT 9 AND 03Fh PRT2 1 6 BIT ADDRESS 8 MOV PRT2 1 A 9 ADD B A SUM INDECIES 8 RRC A NORMALIZE 8 TST B DELAY 10 TST B FOR LOOP 10 TST B 179 10 INV B MACHINE CYCLES 8 MOV BPORT B 7 AND 0F0h B 6 OR A B 7 MOV B BPORT 8 INCW 1 TIMER 1 11 JC LOOP 7 JMP TAKEN TOTAL 179 SETMID E...

Page 113: ...D B0 LSB B1 B2 B3 MSB SECT S2 0F900h PLACE TABLE AT PAGE BOUNDARY TABLE MUST START AT A PAGE BOUNDARY TABLE EQU BYTE 08h 09h 0Ah 0Bh 0Ch 0Ch 0Dh 0Dh BYTE 0Dh 0Eh 0Eh 0Eh 0Eh 0Fh 0Fh 0Fh BYTE 0Fh 0Fh 0Fh 0Eh 0Eh 0Eh 0Eh 0Dh BYTE 0Dh 0Dh 0Ch 0Ch 0Bh 0Ah 09h 08h BYTE 07h 06h 05h 04h 03h 03h 02h 02h BYTE 02h 01h 01h 01h 01h 00h 00h 00h BYTE 00h 00h 00h 01h 01h 01h 01h 02h BYTE 02h 02h 03h 03h 04h 05h ...

Page 114: ...95 System Integrity Check for the TMS370 Microcontroller Products Semiconductor Group Texas Instruments ...

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Page 116: ...ins OTHER LABELS PCCHK entry point RESTART address to branch to if error condition is detected RESTART EQU 7000h SMAX EQU 07fh STACK EQU 07fh PCCHK EQU STSP Store current stack pointer MOV 3 B A Load MSB return CMP 7FFEh A Abort if MSB reset vector JL ABORT JNE PCCHK1 Must be equal for next check MOV 2 B A Load LSB return CMP 7FFFh A Abort if LSB reset vector JL ABORT PCCHK1 CMP STACK 5 B Load bes...

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Page 118: ... III Module Specific Application Design Aids Part III contains six sections RESET Operations 99 SPI and SCI Modules 105 Timer and Watchdog Modules 199 Analog to Digital Modules 309 PACT Module 375 I O Pins 439 ...

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Page 120: ...101 Reset Explanation of Operation and Suggested Designs Michael S Stewart Microcontroller Products Semiconductor Group Texas Instruments ...

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Page 122: ...oscillator fault circuitry causes a system reset if the oscillator is operating below a minimum specified frequency trip point that is typically below 20 KHz but never above 500 KHz When this condition is detected the OSC FLT FLAG P010 4 is set and the reset pin is held low until normal oscillation returns typicallyabout1 8MHz TheOSCFLTFLAGisnotclearedbyanactivereset Therefore oncethedevice attain...

Page 123: ...370 The RC network of 10 kΩ and 0 47 pF provides a power up rise time If this power up rise time is not long enough you can use a larger capacitor However replacing the 10 kΩ resistor with a larger resistor may cause the voltage at the RESET pin to be less than VIH The 2 7 kΩ resistor protects the RESET pin from the capacitor discharging directly into the pin when the pin is pulled low internally ...

Page 124: ... III Module Specific Application Design Aids Part III contains six sections RESET Operations 99 SPI and SCI Modules 105 Timer and Watchdog Modules 199 Analog to Digital Modules 309 PACT Module 375 I O Pins 439 ...

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Page 126: ...107 Using the TMS370 SPI and SCI Modules Kevin L Self Microcontroller Products Semiconductor Group Texas Instruments Contributions by Paul Krause Mark Palmer and Al Lovrich ...

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Page 128: ...RS 232 External hardware and software overhead are reduced by the flexibility and programmability of the interfaces This application report provides examples of hardware interfaces and software routines to illustrate the versatility of the SPI and SCI modules Common applications of these modules will be discussed which may be modified to suit the engineer s specific needs Additional information on...

Page 129: ...tion the SPI can be used to load memory RAM or EEPROM and allow the device to be reprogrammed in socket A block diagram of the SPI is shown in Figure 1 In its simplest form the SPI can be thought of as a fast programmable shift register Data to be transmitted is written to the SPIDAT register and received data is latched into the SPIBUF register to be read Data transmission rates and data formatti...

Page 130: ...data is shifted through the SPIDAT register any data value in SPIDAT is always modified after a transmission even if no new data value has been received into the register The SPIDAT register will contain indeterminate data because no new data has been received The Slave Mode The slave mode is used when the SPI is controlled by another serial device In the slave mode the SPI is dependent on an exte...

Page 131: ...elease the reset Before initiating a data transmission you need to initialize the parameters discussed in the following sections SPI Data Format Transmitting and Receiving Character length is programmable and can be set from one to eight bits by the user This is done by setting SPICCR bits 0 2 to the appropriate values shown in Table 1 If the character length is fewer than eight bits it is importa...

Page 132: ... clock pulse When an external clock is being used slave mode the input clock frequency cannot be greater than SYSCLK 8 to allow the internal clocks to synchronize Table 1 SPI Character Bit Length Char2 Char1 Char0 Character Length 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 8 Table 2 SPI Clock Frequency SPI Bit Rate 2 SPI Clock Frequency 0 0 0 SYSCLK 2 0 0 1 0 1 0 0 1 1 1 0 0 1 0...

Page 133: ...and efficient way to handle the reception or transmission of data The interrupt can be enabled or disabled using the SPI INT ENA bit SPICTL 0 and the interrupt priority set with the SPI PRIORITY bit SPIPRI 6 Whether or not the SPI interrupt is enabled the SPI INT flag SPICTL 6 will be set upon the transmission or reception of a character The SPI INT flag cannot be cleared as it is read only but it...

Page 134: ...evice usually but not necessarily the master sends out an address to other devices in the network that have their TALK bits set to 0 Since reception is not affected all devices receive the transmitted address and compare it to their own addresses If a device matches it sets its TALK bit and begins transmitting data When it finishes the receiving device clears its TALK bit and the network waits for...

Page 135: ...easily implemented in software for the SPI Parity checking involves reserving one bit of the character to be used in setting the total number of 1s in a character as odd or even If you are going to be sending large blocks of data there are coding methods that allow faster data transfer but still ensure data integrity Block checksums and other encoding methods can be found in most books on digital ...

Page 136: ...quate for the following examples shown below Common Equates SPICCR equ P030 SPI Configuration Control Register SPICTL equ P031 SPI Operation Control Register SPIBUF equ P037 Serial Input Buffer SPIDAT equ P039 Serial Data Register SPIPC1 equ P03D SPI Port Control Register 1 SPIPC2 equ P03E SPI Port Control Register 2 SPIPRI equ P03F SPI Priority Control Register ...

Page 137: ...approximately Since only integers are allowed the bit rate should be set to the next highest value such as 4 which is SYSCLK 32 This gives an actual SPI rate of 156 25 kHz which is within the operating range of the shift register The character size is eight bits Routine SETMASTER MOV 0E7h SPICCR SPI reset clock active low 128 8 bits MOV 006h SPICTL Master mode enable TALK disable SPI INT MOV 002h ...

Page 138: ...lobal interrupts MOV 0E7h SPICCR SPI reset clock active low 32 8 bits MOV 001h SPICTL Slave mode TALK disable SPI INT enable MOV 002h SPIPC1 Set SPICLK MOV 022h SPIPC2 Enable SPISOMI SPISIMO pins for SPI MOV 040h SPIPRI SPI interrupts are low priority MOV 067h SPICCR Release SPI RESET EINT Enable global interrupts Insert main part of program here SPI INT will fetch characters when first is detecte...

Page 139: ...a to be transmitted as needed If the character length is less than five bits the routine swaps nibbles to save time The value to be transmitted is stored in the register DATA Routine LJUSTIFY MOV SPICCR NUMBITS Save character length in temp register XOR 0FFh NUMBITS 8 numbits number of shifts AND 007h NUMBITS Clear all bits except character length BTJZ 004h NUMBITS ROLL If 4 shifts needed go to ro...

Page 140: ...nterrupt routine which is called when a character is received If it is the correct address the TALK bit is set SPIDAT is loaded and the TALK bit is cleared once again Routine SPIINTR MOV SPIBUF ADDRESS Store received address CMP MYADDRESS ADDRESS Is it my address JNZ DONE If not ignore transmission OR 002h SPICTL Set TALK bit MOV DATA SPIDAT Load transmit buffer wait for clock from master WAIT BTJ...

Page 141: ...uch as decoders This example interfaces a TMS370C010 microcontroller to a vacuum fluorescent display The only external logic necessary is one TMS0170 VF Display Driver This device is a 33 bit shift register display driver and is especially suited for serial display applications The design uses only SPI and Timer 1 T1 pins so thedesignerdoesnotneedtodedicateanymoreI Opinstothedesign Theschematicsho...

Page 142: ...GMENT 2 B SEGMENT 2 C SEGMENT 2 D SEGMENT 2 E SEGMENT 2 F SEGMENT 2 G SEGMENT 3 A SEGMENT 3 B SEGMENT 3 C SEGMENT 3 D SEGMENT 3 E SEGMENT 3 F SEGMENT 3 G SEGMENT 4 A SEGMENT 4 B SEGMENT 4 C SEGMENT 4 D SEGMENT 4 E SEGMENT 4 F SEGMENT 4 G A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 D 3 D 4 D 5 D 6 D 7 SPISIMO SPICLK T1PWM T1EVT T1IC CR In the example below the display is pulsed periodically to adjust the inten...

Page 143: ...ster values are found from the formulas Compare 1 value Compare 1 value 5 000 000 100 x 16 SYSCLK Frequency refreshes s x prescale divide Compare 2 value intensity x compare 1 value Compare 2 value bright 0 9 x 3125 2812 or 0AFCh Compare 2 value dim 0 4 x 3125 1250 or 04E2h By XORing the bright and dim values together we get the logical difference between the two values XORing the difference with ...

Page 144: ...equ P037 SPIPC1 equ P03D SPIPC2 equ P03E T1CNTRMSB equ P040 T1 register assignments T1CMSBLSB equ P041 T1CMSB equ P042 T1CLSB equ P043 T1CCMSB equ P044 T1CCLSB equ P045 T1CTL1 equ P049 T1CTL2 equ P04A T1CTL3 equ P04B T1CTL4 equ P04C T1PC1 equ P04D T1PC2 equ P04E T1PRI equ P04F Allocate register space for the registers used in the application routine DISPMSB equ R5 High byte of display value DISPLS...

Page 145: ...T MOV 002h SPIPC1 Enable SPICLK out MOV 020h SPIPC2 Set SPISIMO out Set delays for brightness and value updates MOV HI TIMER T1CMSB Load compare 1 register with delay MOV HI TIMER T1CLSB Time between refreshes 10 mS MOV HI BRIGHT T1CCMSB Set display to bright intensity MOV LO BRIGHT T1CCLSB MOV INTERVAL ICOUNT Temp register for interval counter Timer 1 Initialization MOV 001h T1PC1 Set T1EVT as ge...

Page 146: ...JMP MAIN T1 Interrupt Routine This routine pulls the value to be displayed from DISPMSB and DISPLSB converts it to a packed 4 nibble BCD number and shifts the result out through the SPI The routine checks to see whether the routine was called by the timer or the T1C1 pin and clears the appropriate flag DISPMSB and DISPLSB are temporary registers and will not contain their original values upon comp...

Page 147: ... Hex to BCD Conversion Routine CLR DIGIT2 Clear result registers CLR DIGIT0 MOV 16 R3 Set loop count LOOP RLC DISPLSB Shift high bit out RLC DISPMSB Carry contains the high bit DAC DIGIT0 DIGIT0 Double the number then add high bit DAC DIGIT2 DIGIT2 DJNZ R3 LOOP Loop until multiplied 16 times MOV DIGIT0 DIGIT1 Save second digit MOV DIGIT2 DIGIT3 Save third digit SWAP DIGIT1 Swap BCD nibbles SWAP DI...

Page 148: ...cation of next digit register BTJZ 004h DCOUNT NEXTCHAR If 4 characters sent then send another MOV 005h T1PC1 Toggle TlEVT to latch data MOV 001h T1PC1 Pull TlEVT low again OR 001h T1CTL4 Re enable T1IC CR interrupt here This allows delay between recognition of dim bright toggles to debounce switch NOTNOW AND 0DFh T1CTL3 Clear TlCl interrupt flag DONE RTI Return from interrupt Look up table for co...

Page 149: ...130 Set up interrupt vector addresses sect Vectors 07FF4h word DISPLAY T1 interrupt word START All other vectors go to START word START word START word START word START ...

Page 150: ... the field The interrupt routine must do the following Figure 4 Flowchart of Bootstrap Loader Interrupt Service Routine CALL INTx INITIALIZE SPI SET COUNTER TO START OF BLOCK WAIT FOR CHARACTER MOVE CHARACTER TO BLOCK START COUNTER COUNTER COUNTER 1 END OF DATA N Y BRANCH TO START OF BLOCK START EXECUTION The interrupt routine loads the received data into program memory beginning at a specified lo...

Page 151: ...INT2 DX DR CLKX CLKR XF FSX FSR A0 SPISOMI SPISIMO SPICLK INT3 22 54 24 63 64 56 53 25 14 25 23 24 18 In the setup of figure 6 data to and from both devices is clocked using the SPICLK The TMS370 is configured so that receipt of an INT3 signal causes the TMS370 to load the SPIDAT register to start the SPICLK If the TMS320C25 wants to initiate the conversation it pulls INT3 low waits for SPIDAT and...

Page 152: ...8 characters to TMS370 If SPEAK370 0 TMS370 clears INT3 flag TMS370 clears SPEAK370 flag TMS320C25 initiated transmission Ready for next transmission Default TMS320 transmitting Figure 6 shows the timing diagram of the continuous mode of 8 bit data transmission Figure 6 Continuous Mode No Frame Synchronization Pulse SPICLK FSX FSR SPITXD C25 DR C25 DX SPIRXD 370 Data TX Byte 1 370 Data TX Byte 1 3...

Page 153: ...odes of transmission such as C25 s ability to transmit in either 8 bit or 16 bit mode allowscustomizationtotheparametersofthedesiredsystem Theroutinesshowndonotincorporate any checks if both the C25 routine and TMS370 routine try to communicate at the same time When this situation occurs both processors will think that they initiated the communication and ignore the received data If asynchronous c...

Page 154: ...OV 022h SPIPC2 Set SPISIMO SPISOMI out MOV 020h SPIPRI Enable emulator suspend MOV 007h SPICCR Reset SPI data out on rising SPICLK 8 bit characters MOV 001h ADIR Set A0 as output MOV 001h ADATA Set A0 high MOV 01H INT1 Initialize interrupt 1 MOV 01H INT2 Initialize interrupt 2 MOV 01H INT3 Initialize interrupt 3 SBIT0 SPEAK370 Default is TMS370 not speaking SBIT1 FIRSTX Initialize as first Transmi...

Page 155: ...alled when the TMS370 is going to transmit or receive data Do frame sync once FIRSTX INTR3 JBIT0 FIRSTX DATA If NOT the first transmission goto DATA SBIT0 FIRSTX Clear FLAG FIRSTX this is first time MOV 080h SPICCR Set character size 1 bit MOV 000h SPICCR Reset SPI data out on rising SPICLK MOV 000h SPIDAT Transmit dummy pulse to make TMS320 generate FSX FSR sync pulse WAIT1 BTJZ 0040h SPICTL WAIT...

Page 156: ... to START word INTR3 INT3 vector word INTR2 INT2 vector word INTR1 INT1 vector word START Reset vector The source code for the TMS370C25 in this application is as follows sample program for interfacing the TMS370C10 and the TMS320C25 serial ports DRR equ 0 Serial port receive register DXR equ 1 Serial port transmit register IMR equ 4 Interrupt mask register DATA equ 96 General purpose register sec...

Page 157: ...subroutine INT2 is entered the 320 again tells the 370 to start clocking the serial port and the 320 knows that it needs to save the data it receives RXISR lets the processor know when the data has been received XMIT LAC DXR Load data for transmission CALL XMTISR Initiate data transfer to 370 EINT Enable interrupts IDLE Wait for received data do not save RET received data INT2 equ RPTK 40 Give 370...

Page 158: ...RXISR equ Serial receive interrupt EINT Enable interrupts RET XMTISR equ Initiate data transfer to 370 routine RXF Toggle XF flag low causes 370 interrupt NOP NOP NOP SXF and then high to clear only want 370 INT3 RET routine to execute once ...

Page 159: ... hardware a programmable clock for setting the baud rate and frame format parity error circuitry NOTE The TMS370 Family contains two different SCI Modules The SCI1 Module has three external pins SCICLK SCITXD SCIRXD while the SCI2 Module contains two external pins SCITXD SCIRXD See the TMS370 Family User s Guide for more information Figure 7 SCI1 Block Diagram RXST 4 2 FE OE PE RX ERROR SCICTL 3 T...

Page 160: ...S BIT MODE IDLE LINE MODE NORMAL NON MULTIPROCESSOR COMMUNICATIONS START LSB 2 3 4 5 6 7 MSB PARITY STOP ADDR DATA START LSB 2 3 4 5 6 7 MSB PARITY STOP With the exception of the start bit and NRZ formatting all the elements mentioned above are user programmable These are controlled by the SCI communication control register SCICCR 1 Protocols The TMS370 SCI supports two protocols the idle line and...

Page 161: ...atchaframing SCIsynchronization error Adding the extra bit increases the number of bits transmitted per character however and slows the throughput of the serial port The SCI SW RESET Bit The SCI SW RESET bit SCICTL 5 is used to reset the condition of the SCI state machine and operating flags Writing a 0 to this bit sets the operating flags to their reset state and halts the operation of the SCI Th...

Page 162: ...fted out on every shift clock cycle Using the isosynchronous mode gives a data transfer rate 16 times the corresponding asynchronous SCICLK rate but requires an extra line to carry the SCICLK signal The isosynchronous mode is superior to simpler synchronous communications such as the SPI in that you can achieve near synchronous communication speeds but still use formatting to assure data integrity...

Page 163: ... frames This holds whether communications are between two TMS370s or a TMS370 and a different peripheral device The baud rate is set by writing a 16 bit value to the baud rate select registers BAUDMSB and BAUDLSB The equations used to calculate the baud rate register values are shown below Asynchronous baud rate SYSCLK BAUD RATE REG 1 x 32 Isosynchronous baud rate SYSCLK BAUD RATE REG 1 x 2 Table ...

Page 164: ...the protocol and format the receiver checks for transmission errors and loads the data into RXSHF the receiver shift register When the number of bits specified by the SCI character length control bit have been read in the contents of RXSHF are transferred to the receiver data buffer RXBUF and the RXRDY flag is set to show that the data value is ready to be read An SCI receiver interrupt is generat...

Page 165: ...F PARITY OVERRUN OR FRAMING ERRORS SET APPROPRIATE FLAGS RXERROR 1 RX ERROR 1 USER DEFINED ERROR ROUTINES RXENA Yes Yes No No RXSHF RX BUF RXRDY 1 RXWAKE 0 RXSHF DATA LOCATION RXRDY 0 ADDRESS BIT MODE IDLE 11 BITS ADDRESS BIT 1 RXWAKE 1 IS ADDRESS MINE SLEEP 0 SLEEP 1 MORE DATA SLEEP 1 END OF ROUTINE Yes No Yes No Yes Yes No No Yes SHADED SOFTWARE No ...

Page 166: ...smitter buffer TXBUF which clears the TXRDY flag When TXSHF the transmitter shift register is empty the contents of TXBUF are latched into TXSHF and the TXRDY flag is set to indicate the transmitter is ready for a new character Depending on the protocol and format the transmitter formats the data as needed to signal the beginning and end of frames of data ...

Page 167: ...LAY 10 FRAMES ADDRESS TXBUF TXBUF TXSHF TXWAKE WUT TXREADY 1 TXEMPTY 0 TXENA TXSHF SCITXD TXEMPTY 1 TXWAKE 0 MORE DATA TXRDY 1 DATA TXBUF END OF ROUTINE TXBUF TXSHF TXWAKE WUT TXREADY 1 TXEMPTY 0 TXWAKE 0 No TXENA No WUT 1 ADDRESS BIT 1 ADDRESS BIT 0 TXSHF SCITXD TXEMPTY 1 MORE DATA TXRDY 1 DATA TXBUF END OF ROUTINE Yes No No Yes Yes No Yes Yes Yes Yes Yes No No SHADED SOFTWARE ...

Page 168: ...e character as determined by the SCI character length This provides a convenient and efficient way of timing and controlling the operation of the SCI transmitter and receiver The interrupt flags for the transmitter and receiver are TXRDY TXCTL 7 and RXRDY RXCTL 7 respectively The TXRDY flag is set when a character is transferred to TXSHF and TXBUF is ready to receive a new character In addition wh...

Page 169: ...HF 2 No format errors are recognized but BRKDT is 3 Data is shifted into RXBUF but RXRDY is not set 4 RXINT is disabled A block start signal acts like an alarm clock for the sleeping SCI receiver A block start signal signifies that thecurrentsignalisanaddress Intheaddressbitmode thisissignalledbyaddressbit 1 Intheidlemode a block starts when a low bit is detected after an idle period of 10 bits or...

Page 170: ...CITXD FUNCTION bit 0 and the SCITXD DATA DIR 0 will put the pin into an input configuration that will prevent bus conflicts from occurring Choosing the Right Protocol Because no idle period is needed between blocks the address mode is more efficient when sending small blocks of data typically fewer than 10 frames When sending larger blocks however it is usually more efficient to use the idle line ...

Page 171: ... a large amount of data is being received store it in a table and manipulate it later As soon as the receiver interrupt is called move the data out of RXBUF and store it in another register This will prevent new data from overwriting data that is already in RXBUF and causing a receiver overrun Detecting Transmission Errors The advantage of formatting data is the ability to detect communication err...

Page 172: ... Encoding methods such as cyclic redundancy checking CRC or block encoding can be found in most good books on digital communications The checksum method of error checking involves checking parity on a block of data as well as the individual characters What to Do With Transmission Errors Once you get an error what do you do Unfortunately with digital communications there is no easy way to correct b...

Page 173: ...51 SCI operation control register BAUDMSB equ P052 Baud rate select XSB register BAUDLSB equ P053 Baud rate select LSS register TXCTL equ P054 Transmitter interrupt control and status register RXCTL equ P055 Receiver interrupt control and status register RXBUF equ P057 Receiver data buffer register TXBUF equ P059 Transmit data buffer register SCIPC1 equ P05D SCI port control register 1 SCIPC2 equ ...

Page 174: ...ocol 8 bit characters MOV 00h SCICTL SCI SW RESET MOV HI B1200 BAUDMSB Set for 1200 baud 5 MHz MOV LO B1200 BAUDLSB MOV 001h RXCTL Enable SCIRX INT MOV 002h SCIPC2 Set SCIRXD as input MOV 060h SCIPRI SCIRX SCITX interrupts low priority MOV 033h SCICTL Release SCI SLEEP 0 RXENA TXENA Main code here RXINT Receiver interrupt routine BTJZ 004h SCICTL AWAKE If SLEEP 0 do not check address XOR ADDRESS R...

Page 175: ...it even parity asynchronous idle line protocol 8 bit characters MOV HI B1200 BAUDMSB Set for 1200 baud MOV LO B1200 BAUDLSB MOV 001h RXCTL Enable SCIRX INT MOV 002h SCIPC2 Set SCIRXD as input MOV 060h SCIPRI SCIRX SCITX interrupts low priority MOV 032h SCICTL Internal clock TXENA RXENA Main code here CALL XMIT Call subroutine to transmit character More main code here XMIT MOV 01Ah SCICTL Set TXWAK...

Page 176: ... of the RXWAKE flag If it is set then the received character is an address and the ninth bit is set otherwise it is not an address and the ninth bit is 0 Routine B1200 equ 129 MOV 000h SCICTL SCI SW RESET MOV 07Fh SCICCR 1 stop bit even parity asynchronous address bit protocol 8 bit characters MOV HI B1200 BAUDMSB Set for 1200 baud MOV LO B1200 BAUDLSB MOV 001h RXCTL Enable SCIRX INT MOV 022h SCIP...

Page 177: ...ts to talk to it The following code shows how to put a TMS370Cx5x into HALT mode to be awakened upon a SCIRXD interrupt NOTE You must enable interrupts before executing the IDLE instruction or the part will not recover from the low power mode except on a system RESET Routine B1200 equ 129 MOV 00h SCICTL SCI SW RESET MOV 077h SCICCR 1 stop bit even parity asynchronous Idle line protocol 8 bit chara...

Page 178: ...ller For more information about the RS 232 C interface consult the References Section for books on digital communications RS 232 C specifications are vague about the exact uses and protocols associated with the pins This example shows a common format using the CTS clear to send and DTR data terminal ready lines for handshaking The transmitted data and received data lines are used for the actual da...

Page 179: ... 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 2 5 14 7 13 8 15 1 11 10 12 9 3 4 5 15 43 29 28 30 15 mF 15 mF AN7 SCIRXD SCICLK SCITXD TMS370C050 MAX232 RS 232 CONNECTOR GND C1 C1 C2 C2 T1 IN T2 IN R1OUT R2 OUT VCC T1 OUT T2 OUT R1 IN R2 IN GND V V VCC VSS VSS VCC DTR SG CTS RD TD ...

Page 180: ...aud rate select MSB register BAUDLSB equ P053 Baud rate select LSB register TXCTL equ P054 Transmitter int control status register RXCTL equ P055 Receiver int control status register RXBUF equ P057 Receiver data buffer register TXBUF equ P059 Transmit data buffer register SCIPC1 equ P05D SCI port control register 1 SCIPC2 equ P05E SCI port control register 2 Define registers constants used in prog...

Page 181: ...outine RXCHAR When the program is ready to transmit it loads register DATA OUT and calls subroutine TXCHAR MAIN RECEIVE CALL RXCHAR Get next character MOV A DATAIN XMIT MOV DATAOUT A CALL TXCHAR Transmit character JMP MAIN SCI receiver subroutine The subroutine brings CTS high to signal that the TMS370 is ready to receive data then it waits until a character is received After a character has been ...

Page 182: ...lled to make sure the character has been transmitted before continuing TXCHAR BTJZ 080h ADIN TXCHAR Wait for DTR to go high TXWAIT BTJZ 080h TXCTL TXWAIT Wait until previous characters are transmitted out MOV A TXBUF Send out the character RTS Set up interrupt vector addresses sect VECTORS 07FF2h word START No interrupts are used word START All vectors will jump to START word START word START word...

Page 183: ...ardware to control the transmission Because the receive and transmit routines are independent and interrupt driven they can be combined with other routines to expand the uses beyond that of a simple terminal controller The example shown below is the framework for a terminal controller showing the code necessary for receiving from and transmitting to the terminal When the program receives a charact...

Page 184: ...rol register 2 SCIPRI equ P05F SCI priority control register Allocate register space for registers used in program Also mark beginning of spaces to be used by 32 byte data transfer buffers COMSTAT equ R2 Communications status register LOCSTAT dbit 0 COMSTAT X Status from local TKS370 1 Xoff REMSTAT dbit 1 COMSTAT X Status from remote terminal 1 Xoff RXPTR equ R3 Location of last received data in B...

Page 185: ...0Fh BAUDLSB MOV 001h RXCTL Enable SCIRX INT MOV 001h TXCTL Enable SCITX INT MOV 002h SCIPC1 Set SCICLK as function pin MOV 022h SCIPC2 Set SCIRXD SCITXD as input MOV 050h SCIPRI SCIRX INT high priority SCITX INT low priority MOV 033h SCICTL Release SCI internal clock sleep 0 RXENA TXENA Clear data registers CLR COMSTAT Set status flags to XON CLR RXPTR Clear data pointer registers CLR RXPTRI CLR R...

Page 186: ...FFER MOV A DATA NORCVR NOP Massage data for terminal formatting uppercase etc MOV DATA A CALL TXCHAR Place character in TXBUFFER to be transmitted JMP MAIN SCI Receiver Subroutine This routine is called whenever the program is ready to process a character in the receiver buffer RXCHAR BTJO 0FFh RXDIFF CHKXON Any characters in buffer JMP RXCHAR If not wait CHKXON DEC RXDIFF One less character in RX...

Page 187: ...buffer JGE TXCHAR PUSH B MOV TXPTR B INC B Next character to be transmitted BTJZ 020h B NOROLL2 Does TXPTR need to be rolled over MOV 0 B Reset TXPTR to beginning of TXBUFFER NOROLL2 MOV B TXPTR Save new value of TXPTR INC TXDIFF Inc of characters to be transmitted MOV A TXBUFFER B Save character in transmitter buffer POP B Restore value of B OR 001h TXCTL Enable TX interrupt RTS Exit SCI Transmit...

Page 188: ...ne This interrupt routine receives characters and checks for XON and XOFF characters sent by the terminal The received characters are stored in RXBUFFER for the subroutine RXCHAR to manipulate them RXINT PUSH A Save A register contents MOV RXBUF A Grab received character from buffer CMP XON A Was an XON received JNE TRYXOFF SBIT0 REMSTAT Set flag XON received JMP RXDONE TRYXOFF CMP XOFF A Was an X...

Page 189: ...pt routine RXWAIT BTJZ 080h TXCTL RXWAIT Wait until present transmission complete Mov XOFF TXBUF Put XOFF in transmitter buffer SBIT1 LOCSTAT I have sent an XOFF RXDONE POP A Restore A register contents RTI End of receiver interrupt routine Setup interrupt vectors addresses Sect VECTORS 07FF0h word TXINT SCITX interrupt routine word RXINT SCIRX interrupt routine word START All other vectors will j...

Page 190: ... starting the X Off transmission With all this waiting and transmitting inside the RXINT routine it is possible at high SCI speeds that the routine will not be able to finish the current receiver interrupt and get the next character out of RXBUF before it is overwritten There is no simple way around this problem One suggestion is to find the maximum time it takes for the interrupt routine with the...

Page 191: ...e battery operated and serviced infrequently A basic configuration is shown below in Figure 15 The TMS370C050 is connected through the A D port to a variety of analog sensing devices The transmit and receive lines are buffered through external logic to whatever levels are necessary to communicate with the host controller The communications link may be as simple as a direct wire connection or as co...

Page 192: ...timer and counter values is Timebetweenupdates 10 min 600 sec 256 0 5 MHz PRESCALE SYSCLK x T1 value x interval counter For this example x 65104 x 18 The device will periodically update ATABLE where the data is stored Upon receipt of information from the host SCIRXD goes low the remote THS037C050 will come out of STANDBY mode If the received data does not match the internal address the part goes b...

Page 193: ... T1CCMSB equ P044 T1CCLSB equ P045 T1CTL1 equ P049 T1CTL2 equ P04A T1CTL3 equ P04B T1CTL4 equ P04C T1PC1 equ P04D T1PC2 equ P04E T1PRI equ P04E Allocate register space for variables and data table used in the routine ADDRESS equ R2 Temp register for received value ICOUNT equ R3 Counter for number of T1 interrupts before data is sampled for table ATABLE equ R4 Table where A D data is stored before ...

Page 194: ...clock TXENA RXENA T1 Initialization MOV TIMEMSB TlCMSB Set timer values MOV TIMELSB TlCLSB MOV 040h T1PRI Set T1 interrupts to low priority MOV 010h T1CTL4 Dual compare disable interrupts MOV 007h T1CTL1 System clock 256 MOV 001h T1CTL3 Disable T1 interrupts clear flags MOV 001h T1CTL2 Disable overflow interrupts reset Tl MOV INTERVAL ICOUNT Initialize counter Mov 200 B Initalize the stack pointer...

Page 195: ... ATABLE 1 B Store data in ATABLE MOV INTERVAL ICOUNT Restore counter DONE RTI End of service routine SCI Receiver Interrupt Routine This routine is called when the part receives a low pulse on the SCIRX pin The received datum is compared against an internal address to see if the device was addressed If so the routine transmits one character indicting the number of bytes to be transmitted The routi...

Page 196: ...last character to be sent RXDONE RTI Exit interrupt routine and go back into STANDBY mode Set up interrupt vectors sect VECTORS 07FF2h word RXINT SCIRX interrupt routine word TIMERINT T1 interrupt routine word START All other vectors will jump to START word START word START word START word START ...

Page 197: ...RITY SPI BIT RATE2 SPI BIT RATE1 SPI BIT RATE0 SPI CHAR2 SPI CHAR1 SPI CHAR0 SPICTL 1031h P031 RECEIVER OVERRUN SPI INT FLAG MASTER SLAVE TALK SPI INT ENA 1032h P032 to to Reserved 1036h P036 SPIBUF 1037h P037 RCVD7 RCVD6 RCVD5 RCVD4 RCVD3 RCVD2 RCVD1 RCVD0 1038h P038 Reserved SPIDAT 1039h P039 SDAT7 SDAT6 SDAT5 SDAT4 SDAT3 SDAT2 SDAT1 SDAT0 103Ah P03A to to Reserved 103Ch P03C SPIPC1 103Dh P03D S...

Page 198: ...LEEP TXENA RXENA BAUD MSB 1052h P052 BAUDF MSB BAUDE BAUDD BAUDC BAUDB BAUDA BAUD9 BAUD8 BAUD LSB 1053h P053 BAUD7 BAUD6 BAUD5 BAUD4 BAUD3 BAUD2 BAUD1 BAUD0 LSB TXCTL 1054h P054 TXRDY TX EMPTY SCI TX INT ENA RXCTL 1055h P055 RX ERROR RXRDY BRKDT FE OE PE RXWAKE SCI RX INT ENA 1056h P056 Reserved RXBUF 1057h P057 RXDT7 RXDT6 RXDT5 RXDT4 RXDT3 RXDT2 RXDT1 RXDT0 1058h P058 Reserved TXBUF 1059h P059 T...

Page 199: ...AUD1 BAUD0 LSB TXCTL 1054h P054 TXRDY TX EMPTY SCI TX INT ENA RXCTL 1055h P055 RX ERROR RXRDY BRKDT FE OE PE RXWAKE SCI RX INT ENA 1056h P056 Reserved RXBUF 1057h P057 RXDT7 RXDT6 RXDT5 RXDT4 RXDT3 RXDT2 RXDT1 RXDT0 1058h P058 Reserved TXBUF 1059h P059 TXDT7 TXDT6 TXDT5 TXDT4 TXDT3 TXDT2 TXDT1 TXDT0 105A h P05A 105B h P05B Reserved 105C h P05C 105D h P05D SCIPC2 105E h P05E SCITXD DATA IN SCITXD D...

Page 200: ...icated with high voltage PMOS technology 40 pin DIP and 44 pin PLCC plastic packages are available Functional Description Architecture The TMS0170 shown in Figure 16 as a block diagram consists of a 34 bit data shift register a 33 bit data latch and 33 VF drivers A bit pattern is shifted into the TMS0170 using the clock input then transferred to the data latch using the load enable input The blank...

Page 201: ...n the TMS0170 and the digital logic consists of four lines a clock in line a data in line and a load enable line and a Blank input Data Input Determines what data value is loaded into the data shift register This data can then be latched to the output drivers upon a valid load enable input A latched high level will turn the output driver on A latched low level will turn the output driver off Clock...

Page 202: ...IT 33 LC OUTPUT BIT 5 LC OUTPUT BIT 6 LC OUTPUT BIT 7 LC OUTPUT BIT 28 LC OUTPUT BIT 27 LC OUTPUT BIT 31 LC OUTPUT BIT 18 LC OUTPUT BIT 32 VDD BLANK LOAD ENABLE LC OUTPUT BIT 20 LC OUTPUT BIT 25 LC OUTPUT BIT 24 LC OUTPUT BIT 19 LC OUTPUT BIT 12 LC OUTPUT BIT 17 LC OUTPUT BIT 16 LC OUTPUT BIT 11 LC OUTPUT BIT 4 LC OUTPUT BIT 9 LC OUTPUT BIT 8 LC OUTPUT BIT 3 LC OUTPUT BIT 29 LC OUTPUT BIT 26 LC OU...

Page 203: ...vel Output Voltage low current drivers VSS 9 5 V IOH 1 5 mA Vss 0 3 V VOH High Level Output Voltage high current drivers VSS 9 5 V IOH 30 0 mA VSS 2 5 V VOH High Level Output Voltage DATA OUT output VSS 9 5 V IOH 500 µA VSS 5 0 V VOL Low Level Output Voltage DATA OUT output VSS 9 5 V IOL 1 µA VSS 9 5 V IOL 500 µA VDD 0 4 VDD 5 0 V V VOL Low Level Output Voltage DATA OUT output VSS 9 5 V IOL 1µA VD...

Page 204: ...s or writes In the SCI the temporary registers are TXBUF and RXBUF They are used to hold data while transmitting or receiving and TXSHF or RXSHF are being used speeding up data transfer and reducing the possibility of transmitter or receiver overruns frame Thebasicpacketofserialcommunication Ittypicallycontainsonestartbit onetoeightbitsofdata and one or two stop bits It may also contain a parity b...

Page 205: ...mber depending on whether odd or even parity is used protocol The rules of communication and data format in a communications link between two devices shift clock cycle One cycle of the SCI clock that gates one bit of data For isosynchronous communications one shift clock cycle gates one bit of data or format information In the asynchronous mode 16 shift clock cycles are needed per bit of informati...

Page 206: ...g Center 1984 Schwartz Mischa Information Transmission Modulation and Noise McGraw Hill Book Company 1980 T I Microcontroller Applications Group TMS370 Family User s Guide Texas Instruments Technical Publishing 1996 T I Digital Signal Processing Applications Group TMS320C25 User s Guide Texas Instruments Technical Publishing 1986 ...

Page 207: ...188 ...

Page 208: ...189 Fast Method to Determine Parity With the TMS370 Microcontroller Products Semiconductor Group Texas Instruments ...

Page 209: ...190 ...

Page 210: ... Status bit result to calling routine Routine STEP 1 SUBROUTINE Byte bits 7654 3210 TO FIND XOR 7654 MSB above EVEN PARITY xxxx ABCD STEP 2 AB CD XOR AB MS bits above xx ab STEP 3 a b XOR a MS bit x P answer TEXT 7000h Absolute start address PARITY MOV A B Duplicate the target byte SWAP A Line up the ms nibble with the ls nibble XOR B A Exclusive OR the nibbles to get a nibble answer MOV A B Dupli...

Page 211: ...192 ...

Page 212: ...193 Automatic Baud Rate Calculation With the TMS370 Microcontroller Products Semiconductor Group Texas Instruments ...

Page 213: ...194 ...

Page 214: ...smit and receive data signals must be converted to RS 232 levels the 75 188 and 75189 devices provide this function In the asynchronous mode the clock signal does not need to be transmitted but is generated locally at both ends Figure 1 SCI RS 232 Interface Example TMS370 TTL Level SCITXD SCIRXD 75189 5 V 75188 TX Out RX In TTL Level 12 V 12 V SCI Control Registers TheSCIiscontrolledandaccessedthr...

Page 215: ...N SCIRXD DATA OUT SCIRXD FUNCTION SCIRXD DATA DIR SCIPRI 105Fh P05F SCI STEST SCITX PRIORITY SCIRX PRIORITY SCI ESPEN Automatic Baud Rate Calculation The automatic baud rate routine automatically calculates the baud for the SCI port by timing the length of the start bit This eliminates the need for external select switches which can cause confusion The routine converts the SCIRXD pin to a general ...

Page 216: ...Wait for a start bit to go low WAITBIT INC A Dummy gives 32 clock states 1 min baud INCW 1 COUNT Increment counter BTJZ 8 SCIPC2 WAITBIT Wait until start bit ends ASCII char odd SETUP INCW 1 COUNT One less than count into baud reg MOV COUNT BAUDLSB since the SCI starts from count 0 MOV COUNT 1 BAUDMSB Initialize baud registers MOV 22h SCIPC2 Enable RX and TX pins MOV 2 SCIPC1 Enable SCLK pin if ne...

Page 217: ...t routine can use 50 of the ASCII values all odd ASCII values Add a routine to check the parity of the incoming character and set the parity of the SCI port accordingly Again this means a limited number of characters will correctly autobaud the routine As an accuracy check add routines to compare the count of another bit in the character to the start bit count Again you must choose the correct cha...

Page 218: ... III Module Specific Application Design Aids Part III contains six sections RESET Operations 99 SPI and SCI Modules 105 Timer and Watchdog Modules 199 Analog to Digital Modules 309 PACT Module 375 I O Pins 439 ...

Page 219: ...200 ...

Page 220: ...201 Using the TMS370 Timer Modules Microcontroller Products Semiconductor Group Texas Instruments ...

Page 221: ...202 ...

Page 222: ...se concepts may be adapted and applied to fit the specific needs of your individual project AdditionalinformationforT1andT2nmaybefoundintheTMS370FamilyUser sGuide Sections 7 and 8 Table 1 TMS370 Family Timer Module Capabilities System Requirements Timer Resources Real Time System Control Interval Timers with Interrupts Input Pulse Width Measurement Pulse Accumulate or Input Capture Functions Exter...

Page 223: ... and a 16 bit watchdog timer WD Additional functions of the T1 module not illustrated in Figure 1 include the interrupts and l O pins Figure 1 Timer Block Diagram ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ 8 Bit Prescale MUX MUX ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ Edge Detect 16 Bit Capture Compare Register 16 Bit Counter 16 PWM Toggle 16 Bit Compare Register 16 Bit WD Counter Third Timer T1IC CR Pin T1EVT Pin ...

Page 224: ...16 prescale tap System clock with 64 prescale tap System clock with 256 prescale tap System clock off timer not running The clock sources may be independently selected for T1 and the WD For example you could select the event input clock source for T1 while the WD uses the system clock with 64 prescale tap Figure 2 T1 Prescaler Clock Source Prescale T1EVT Pin System Clock 4 16 64 256 T1 Select WD S...

Page 225: ...ting in the capture compare mode The output compare function is used to trigger an action such as toggling the T1PWM pin when the contents of a compare register equal the present value of the counter register The external edge detection function is used to trigger an action such as loading the capture register and occurs when an appropriate external edge is present on the T1IC CR pin This function...

Page 226: ... T1 module provides up to five different interrupt flags depending on the mode of operation The actions that trigger an interrupt are as follows External edge detection input capture An active transition on the T1IC CR pin will cause the T1EDGE INT FLAG bit T1CTL3 7 to be set if the T1EDGE DET ENA bit T1CTL4 0 is set In the dual compare mode this action can reset the T1 counter if the T1CR RST ENA...

Page 227: ...al compare mode of operation Counteroverflow WhentheT1counteroverflowsfrom0FFFFhto0000h theT2nOVRFLINT FLAG bit T1CTL2 3 is set WD overflow The WD has overflowed and the WD OVRFL FLAG bit T1CTL2 5 is set A system reset occurs if the WD OVRFL RST ENA bit T1CTL2 7 is enabled Also an interrupt without system reset can occur when the WD OVRFL RST ENA bit is cleared and the WD OVRFL INT ENA bit T1CTL2 ...

Page 228: ...ctions are as follows T1EVT This pin may be used as an external clock input to the prescaler clock source block Input frequency may not exceed SYSCLK 2 T1IC CR Depending on the mode of operation this pin may be used to input an external signal to trigger loading of the capture register toggle the T1PWM output pin reset the counter or generate an interrupt T1PWM The T1 function of this pin is to ou...

Page 229: ... Prescaler clock source 16 bit counter 16 bit 16 Compare Compare Reset T1C1 RST ENA T1 SW RESET Edge select T1EDGE DET ENA Output enable capture compare register MSB LSB MSB LSB T1CR OUT ENA T1IC CR T1EDGE POLARITY Toggle 16 bit compare MSB LSB register T1CC 15 0 T1C1 INT FLAG T1CTL3 0 T1CTL3 5 T1C1 INT ENA T1C2 INT FLAG T1CTL3 1 T1CTL3 6 T1C2 INT ENA T1 OVRFL INT FLAG T1CTL2 4 T1CTL2 3 T1 OVRFL I...

Page 230: ...pare mode is shown in Figure 7 Figure 7 Capture Compare Mode for T1 T1CTL4 2 16 Compare Edge select T1IC CR T1EDGE POLARITY T1EDGE DET ENA Prescale clock source 16 bit counter MSB LSB T1CNTR 15 0 Reset T1C1 RST ENA T1 SW RESET T1CTL2 0 T1CTL4 4 T1PC2 3 0 T1CTL4 0 T1EDGE INT FLAG T1EDGE INT ENA T1CTL3 7 T1CTL3 2 T1 OVRFL INT FLAG T1 OVRFL INT ENA T1CTL2 3 T1CTL2 4 T1C1 INT FLAG T1C1 INT ENA T1CTL3 ...

Page 231: ... Figure 8 contains a 16 bit counter a 16 bit compare register and a 16 bit capture compare register just like T1 T2n also contains an additional capture register T2n provides input capture output compare timer overflow and external event functions You can choose either the dual compare mode or the dual capture mode of operation for T2n depending on the needs of your application Thebasicfunctionsof...

Page 232: ...re register matches the value of the T2n counter the T2nC2 INT FLAG bit T2nCTL2 6 is set This is true for the dual compare mode of operation only Counter overflow When the T2n counter overflows from 0FFFFh to 0000h the T2n OVRFL INT FLAG bit T2nCTL1 3 is set T2n I O Pins The T2n module includes three I O pins which can be dedicated for timer functions or as general purpose I O pins Their names and...

Page 233: ... as well as one compare register In this mode the capture compare register is configured as a capture register The two capture registers may be used for pulse width measurement and timing and the compare register can be used to generate periodic interrupts A block diagram of T2n in the capture compare mode is shown in Figure 10 Figure 9 Dual Compare Mode for T2n 16 T2nC 15 0 T2nCTL2 1 T2nCTL3 2 T2...

Page 234: ...ster 1 T2nC 15 0 16 bit compare MSB LSB register T2n PRIORITY Level 1 Int Level 2 Int 1 T2nCTL1 3 T2nCTL1 4 16 bit capture MSB LSB register 2 T2nIC 15 0 Edge 2 select T2nIC2 CR T2nPC2 7 4 T2nCTL3 1 Edge 1 select T2nIC1 CR T2nCTL3 2 T2nCTL3 0 16 T2nEDGE1 POLARITY T2nEDGE1 DET ENA T2nEDGE2 DET ENA T2nEDGE2 POLARITY T2nC1 INT FLAG T2nC1 INT ENA T2n OVRFL INT FLAG T2n OVRFL INT ENA T2nEDGE1 INT FLAG T...

Page 235: ...ere SYSCLK internal operational frequency PS 1 4 16 64 or 256 depending on the prescale tap selected Table 2 gives the real time counter overflow rates for various SYSCLK and prescaler values Please note that the value shown must be divided by two for the WD if the WD OVRFL TAP SEL bit T1CTL1 7 is set see Section 7 3 in the TMS370 Family User s Guide Table 2 T1 Module Counter Overflow Rates SYSCLK...

Page 236: ...YSCLK 5 MHz Time T1 Compare Register Value N Error Seconds mSeconds Prescale Decimal Hex Error See Note 0 0005 0 5 None 2499 009C3h 0 000 0 001 1 None 4999 01387h 0 000 0 002 2 None 9999 0270Fh 0 000 0 005 5 None 24999 061A7h 0 000 0 01 10 None 49999 0C34Fh 0 000 0 02 20 4 24999 061A7h 0 000 0 05 50 4 62499 0F423h 0 000 0 1 100 16 31249 07A11h 0 000 0 2 200 16 62499 0F423h 0 000 0 5 500 64 39062 0...

Page 237: ...own below Maximum counter duration seconds 216 SYSCLK Counter resolution SYSCLK where SYSCLK internal operational frequency Table 4 gives the real time counter overflow rates for various SYSCLK values Table 4 T2n Module Counter Overflow Rates SYSCLK Frequency MHz Timer Overflow Rates 20 0 13 11 ms 12 0 21 85 ms 8 0 32 77 ms 5 0 52 43 ms 3 579 73 23 ms 2 0 131 07 ms ...

Page 238: ...are register values to achieve various desired timings Table 5 T2n Compare Register Values SYSCLK 5 MHz Time T2n Compare Register Value N Seconds mSeconds Decimal Hex Error See Note 0 0005 0 5 2499 009C3h 0 000 0 001 1 4999 01387h 0 000 0 002 2 9999 0270Fh 0 000 0 005 5 24999 061A7h 0 000 0 010 10 49999 0C34Fh 0 000 0 013 13 64999 0FDE7h 0 000 NOTE error induced by the T2n formula This error margi...

Page 239: ... compare 2 register MSB T1CCL EQU P045 T1 Capture 1 compare 2 register LSB T1CTL1 EQU P049 T1 Control register 1 T1CTL2 EQU P04A T1 Control register 2 T1CTL3 EQU P04B T1 Control register 3 T1CTL4 EQU P04C T1 Control register 4 T1PC1 EQU P04D T1 Port control 1 T1PC2 EQU P04E T1 Port control 2 T1PRI EQU P04F T1 Priority control T2ACNTRM EQU P060 T2A Counter MSB T2ACNTRL EQU P061 T2A Counter LSB T2AC...

Page 240: ...s the value C34Fh into the T1 compare register putting the MSB value in first All output pins associated with T1 are set as general purpose input pins since their T1 pin functions are not needed for this application The system clock is chosen as the T1 clock source while the watchdog prescale remains unchanged The program then resets the counter clears all interrupt flags and enables the T1C1 inte...

Page 241: ...e and cause T1 to reset on compare equal MOV 00000001b T1CTL3 Clear any pending interrupt flags and allow the compare 1 flag to cause an interrupt AND 11110000b T1CTL1 Select the system clock as timer clock source and leave the WD unchanged MOV 00000001b T1CTL2 Reset the counter could enable WD here EINT Begin interrupting main program MAIN Execute main program here TIMER 1 INTERRUPT SERVICE ROUTI...

Page 242: ... compare register putting the MSB value in first The T1PWM pin is set to the PWM output function and the other T1 pins are set to general purpose input pins since their T1 pin functions are not needed for this application The system clock is chosen as the T1 clock source while the WD prescale remains unchanged The program then resets the counter clears all interrupt flags and disables all T1 inter...

Page 243: ...able T1PWM pin initial output value selected by bit 6 T1IC CR is general purpose input pin MOV 01010000b T1CTL4 Select dual compare mode enable PWM toggle and cause T1 to reset on compare equal AND 11110000b T1CTL1 Select the system clock as timer clock source and leave the WD unchanged MOV 00000000b T1CTL3 Clear and disable all interrupts MOV 00000001b T1CTL2 Reset the counter could enable WD her...

Page 244: ...re register gets used to provide the high pulse period t2 while the first compare register is used to provide the 1 ms period t1 The program loads the value 1387h into the T1 compare register to control the 1 ms period t1 and 03E7h into the T1 capture compare register to control the t2 pulse width Both compare registers are enabled to toggle the output pin to give the proper pulse signal Once the ...

Page 245: ... MOV 01110000b T1CTL4 Select dual compare mode enable toggle function of compare registers 1 and 2 and cause T1 to reset on C1 equal AND 11110000b T1CTL1 Select the system clock as timer clock source and leave the WD unchanged MOV 00000001b T1CTL2 Reset the counter could enable WD here MOV 00000000b T1CTL3 Clear and disable all interrupts MOV 01100000b T1PC2 Enable T1PWM pin initial output value s...

Page 246: ...in this routine while the capture compare register controls the varying duty cycle t2 TheT1serviceroutineisenteredeachtimethecompareregisterequalflaggetsset every1 msinthisexam ple The main program is required to load any new values for the PWM duty cycle into the HIDC and LODCworkingregisters TheT1serviceroutineisonlyenabledwhenevertheHIDC LODCregisterpairis updated and the T1C1 interrupt is enab...

Page 247: ...is a general purpose input EINT Enable interrupts MAIN Execute main program here Any updates to the PWM duty cycle registers HIDC LODC need to be done here UPDATE MOV 01h T1CTL3 Allow the compare flag to cause a timer interrupt only when the duty cycle HIDC LODC registers have been altered Timer 1 Interrupt Routine to follow T1INT MOV 00000011b T1CTL1 Stop T1 if an update has been made MOV 0000000...

Page 248: ...le In the PWM 2 example the pro gram changes the pulse width by varying the value in the capture compare register In this PPM example the program varies the frequency of the pulses by changing the value in the compare register T1CM T1CL For the cleanest transition clear the compare 1 equal flag and wait until that flag gets set again before putt ing a new value into the compare register This will ...

Page 249: ...he counter could enable WD here EINT Enable interrupts MAIN Execute main routine here Any updates to the PPM frequency registers HIFREQ LOFREQ will need to be done here UPDATE MOV 01h T1CTL3 Allow the compare flag to cause a timer interrupt only when the duty cycle HIFREQ LOFREQ registers have been altered T1INT MOV 00000000b T1CTL3 Clear the T1 compare 1 interrupt flag and disable the T1 compare ...

Page 250: ... compare mode of operation The interrupt flags are cleared and a falling edge on the T1IC CR pin is enabled to cause an interrupt The pulse accumulation clock source is chosen and the counter is then reset The counter does not start until the pulse signal goes high and stops counting when the signal goes back low The interrupt routine checks for the end of the pulse or a counter overflow If the in...

Page 251: ...cause an interrupt MOV 00010001b T1CTL2 Reset the counter clear and enable the the overflow interrupt Could enable WD here EINT Enable interrupts MAIN Main routine here T1 interrupt routine to follow T1INT BTJO 08h T1CTL2 OVERFLW Was this interrupt caused by overflow AND 0F7h T1CTL2 Yes jump to OVERFLW MOV T1CNTRL STOREL No load the value in the T1CNTRL MOV T1CNTRM STOREM registers LSB first into ...

Page 252: ...crement the counter instead of the system clock as in the previous example Because clock continues to run after measure goes low the timer module will run in the capture compare mode and use the 16 bit cap ture compare register to store the value of the counter the instant that measure goes low One condition can occur when a counter overflow happens at almost exactly the same time the measure sign...

Page 253: ...ow interrupt WD can enable here EINT Interrupt routine to follow T1INT Interrupt routine BTJZ 08h T1CTL2 PULSELO Was interrupt caused by a low pulse AND 0F7h T1CTL2 No clear overflow flag then increment INC STOREOF the overflow register STOREOF RTI PULSELO MOV T1CCL STOREL YES load the value in the capture register LSB first into the STORE MOV T1CCM STOREM registers BTJZ 08h T1CTL2 NOOVER Was ther...

Page 254: ...he only program intervention needed to do this function If the pulse length becomes greater than one overflowvalueplus1ms thePWMwilltoggleandmaycorrupttheoutput Theoverflowtimeforthisvalue of a prescaler is about 54 ms Change the prescaler to a higher value if a greater range is needed One Shot Routine Single cycle should be under 1 timer overflow TRIAC MOV 04h T1CM Value to give 1 ms with 5 MHz S...

Page 255: ... de tects a rising edge The software could be too slow to react to this condition which is only a few microse conds wide so the overflow interrupt remains active When the circuit detects the rising edge of the first signal the processor stores the capture register value into a register pair The processor then keeps track of the overflows which happen about every 13 1 ms with a 5 MHz SYSCLK signal ...

Page 256: ...TIME2L Get 2nd capture latch value LSB and store it MOV T2AICM TIME2M Get 2nd capture latch value MSB and store it BTJZ 08h T2ACTL1 NOOVER Was there an overflow just now CMP 0FFh TIME2M If overflow and pulse low which came first JEQ NOOVER If FFxxh overflow happened after pulse low INC TIME20F If 00xxh overflow happened first increment register AND 0F6h T2ACTL1 Clear overflow interrupts NOOVER MOV...

Page 257: ...interrupt was caused by the input rising or the output falling by checking the C1 flag If the input rising caused the interrupt the program quickly switches the clocking source from pulse accumulation to the system clock If the input signal goes low before this switch is made then the output pulse will be slightly delayed After it switches the clock source the routine enables the PWM to toggle at ...

Page 258: ...l compare mode look for rising edge on T1IC CR pin and enable edge detection MOV 04h T1CTL3 Clear interrupts and enable T1IC CR edge interrupts MOV 71h T1CTL1 Setup WD clock source pulse accumulator MOV 01h T1CTL2 Reset the counter could enable WD here EINT MAIN Main routine goes here T1INTERR T1 interrupt routine to follow BTJO 20h T1CTL3 ENDPUL Jump if at end of pulse C1 flag 1 MOV 70h T1CTL1 Co...

Page 259: ...initialize the WD to generate a system reset do the following 1 Select the appropriate clock source and WD overflow tap select bits T1CTL1 4 5 6 and 7 2 Clear the WD OVRFL INT FLAG bit T1CTL2 5 This bit must be cleared in order to receive WD generated resets 3 Set the WD OVRFL RST ENA bit T1CTL2 7 Once this bit is set only a power up reset can clearit Forthisconditiontooccur VCC mustfalltosomewher...

Page 260: ...ld incorporate circuitry to cause a RESET when VCC is out of spec See Figure 11 If a reset occurs the RESET subroutine needs to determine if the reset was caused by the WD or not by checking the WD OVRFL INT FLAG T1CTL2 5 If the reset was caused by the WD the WD OVRFL INT FLAG bit T1CTL2 5 must be cleared in order to receive additional WD resets ...

Page 261: ...242 Figure 11 Typical Power Up Down Circuit 10 kΩ VCC 2 7 kΩ To other devices resets 0 47 µF Manual reset Reset in Reset out TMS370 ...

Page 262: ...16 bits in length and the full 8 bit prescale tap is used If a reset occurs the reset subroutine needs to determine if the reset was caused by the WD or not by checking the WD OVRFL INT FLAG T1CTL2 5 Routine INITWD MOV 00h P048 Reset the WD while in the general purpose timer mode MOV 70h P049 Select prescale according to program needs MOV 88h P04A Lock the WD in the WD reset mode MAIN1 MOV 55h P04...

Page 263: ...4 before an interrupt routine occurs a set number of times 30 in this example If the counter register is not cleared the interrupt service writes an invalid data byte to the WDRST key register which causes a system reset 2 A periodic interrupt routine must be entered before the WD completely times out or a system reset will occur Also each time the interrupt routine is entered the counter register...

Page 264: ...er values used in the following routine R4 used as a counter CLR WDCOUNT R5 used as the storage register for the next MOV 0AAh WDSTORE write to WDRST MAIN CLR WDCOUNT Clear the register before interrupt routine increments it past the value 30 The register can be cleared at several points in a program if necessary INTERR Interrupt routine INC WDCOUNT Increment the counter register each interrupt ro...

Page 265: ...ntil a power down If a program does not use the WD circuit then take the following actions to avoid the continuous reset condition 1 Assure the RESET pin is low during power up and oscillator start up 2 Write x011xxxxb to T1CTL1 P049 to halt clocking to the WD circuit 3 Do not clear or write a zero to the WD overflow interrupt flag P04A 5 Consider the read modify write actions of the AND and XOR i...

Page 266: ... is continually loaded into the T1 compare register during the algorithm any changes to the these registers between writes to the compare register will cause the compare equal interrupt period to change If the value of the MSCOMP LSCOMP register pair decreases the T1 interrupt period decreases and the motor steps faster If the value of the MSCOMP LSCOMP register pair increases the T1 interrupt per...

Page 267: ...VCC VSS MC A5 A7 A4 A6 U1 EN DIR EN DIR EN DIR EN DIR U5 B U4 A U3 B U2 A 10 20 V VCC GND 10 20 V VCC GND 10 20 V VCC GND 10 20 V VCC GND XTAL2 XTAL1 OUT OUT OUT OUT A A B B U1 TMS370 Family Microcontroller U2 U3 SN75603 Peripheral Drivers U4 U5 SN75604 Peripheral Drivers ...

Page 268: ... Detected Is Motor Speed Max Is STEPCT Flag 0 Is Motor Speed Min Decrease the Motor Speed to the Min Value Change Motor Rotation Direction and Start Again Y Y Y N N N Begin T1 Interrupt Routine Did T1EDGE Flag Cause Interrupt Did T1C2 Flag Cause Interrupt T1C1 Caused Interrupt Clear and Re Enable T1 Compare Register Flag Is Motor Direction Forward Output the Motor Drive on Port A Set the STEPCT Fl...

Page 269: ...1 port control register 2 T1CTL1 equ P049 T1 control register 1 T1CTL2 equ P04A T1 control register 2 T1CTL3 equ P04B T1 control register 3 T1CTL4 equ P04C T1 control register 4 T1PRI equ P04F T1 priority control register text 7000h Begin initialization Set up stack pointer to begin at R10 Use MS nibble of Port A as the stepper motor drive port Initialize registers to their start values Initialize...

Page 270: ...ue in the T1 compare register Also change direction when the minimum speed has occurred FASTER BTJZ 01 STEPCT FASTER Execute acceleration program here CLR STEPCT Clear the STEPCT rev counter register INCW 80h LSCOMP Decrease the STORE register pair by 80h BTJO 0F7h MSCOMP UPDATE Has the maximum desired speed been reached True when MSCOMP LSCOMP 0880h No update the T1 compare register INC FLAG Yes ...

Page 271: ... LOAD MOV A ADATA into the port A data register forward direction DJNZ B FINIS Optional Decrement the cycle register MOV 04 B count and reload with 4 if zero SETREV INC STEPCT Set the STEPCT rev counter register FINIS RTI Return to the main routine EDGE MOV 01100111b T1CTL3 Clear the T1IC CR interrupt flag reenable all interrupts Execute interrupt code An interrupt routine for a valid signal on th...

Page 272: ...253 word START All other interrupt vectors point to word START the reset vector word START word START word START end ...

Page 273: ...d by the compare registertogeneratea100 msinterruptperiodwitha5 MHzSYSCLKis07A11h Seepage217forformula and look up table The application software uses five registers to keep track of hours minutes seconds tenths of seconds and an AM PM mode flag Additional code and circuitry may be added for external time setting control and calendar application requirements See page 258 The flowchart for the appl...

Page 274: ...tine Wait for an Interrupt Enter T1 Interrupt Routine Clear and Reenable the T1C1 Flag Increment the TENTH Register Does Time 1 s Does Time 1 min Reload the TENTH Register and Increment the Seconds Register Clear the Seconds Register and Increment the Min Register Does Time 1 hour Clear the Minutes Register and Increment the Hour Register Have 12 Hours Elapsed Set the Hour Register to 1 Toggle the...

Page 275: ...acy of clock Set up Equate table for peripheral file registers which will be used in the routine T1CM EQU P042 T1C1 register MSB T1CL EQU P043 T1C1 register LSB T1PC1 EQU P04D T1 port control register 1 T1PC2 EQU P04E T1 port control register 2 T1CTL1 EQU P049 T1 control register 1 T1CTL2 EQU P04A T1 control register 2 T1CTL3 EQU P04B T1 control register 3 T1CTL4 EQU P04C T1 control register 4 T1P...

Page 276: ...e main program Begin your main routine here The jump loop shown is for demonstration only MAIN JMP MAIN T1C1 interrupt service routine to follow T1INT MOV 01h T1CTL3 Clear the C1 flag DJNZ TENTH END Check to see if a second has gone by if MOV 0Ah TENTH not RTI if so continue routine DAC 01 SEC Add a decimal 1 to SEC then see if CMP 060h SEC 60 seconds have elapsed JNE END If not return to main pro...

Page 277: ...0 YEAR100 equ R11 Century FLAG register Incremented on 100 year intervals 2 New stack pointer value and register initialization START MOV l2 B The stack needs to start at 12 LDSP or greater CLR TIME Clear TENTHS CLR TIME l Clear SECONDS CLR TIME 2 Clear MINUTES CLR TIME 3 Clear HOURS MOV 1 TIME 4 Set DAYS to 1 MOV l TIME 5 Set MONTHS to 1 MOV 89 TIME 6 Set YEARS to 1989 CLR TIME 7 Clear the centur...

Page 278: ...leap year jump to NORMAL CMP 28 1 A If leap year is it Feb 29th yet JMP DODAYS NORMAL CMP DAYS 1 B A If month is not Feb is it maxed out yet DODAYS JLO RESTOREB If not restore index and go to DONE DONEMON POP B If so restore index and go to NEXT JMP NEXT Exit to next time unit 4 New look up tables required for routine MAX BYTE 09 59 59 23 31 12 99 Maximim values for TENTH SECOND MINUTE HOUR DAY MO...

Page 279: ...t period with a 5 MHz SYSCLK is 04C4Ah with a 256 prescale See page 217 for formula and look up table This counter application is designed to measure an input signal from 1 Hz to approximately 60 kHz A series of three registers keeps a decimal count of the number of pulses seen on the T1IC CR pin until the compare equal interrupt is detected After each T1 compare equal interrupt the values in the ...

Page 280: ...1 control register 3 T1CTL4 equ P04C T1 control register 4 T1PC1 equ P04D T1 port control register 1 T1PC2 equ P04E T1 port control register 2 T1PRI equ P00F T1 priority control register Begin initialization Set up stack pointer to begin at R10 Initialize registers to their start values Initialize T1 operation text 7000h Program start location START MOV 10 B Initialize the stack pointer to begin a...

Page 281: ...register does not roll RTI over carry 0 then return to the main program MID DAC 0 COUNTM If carry 1 then COUNTM COUNTM 1 JC HIGH If the mid count register does not roll RTI over C 0 then return to the main program HIGH DAC 0 COUNTH If carry 1 then COUNTH COUNTH 1 JNC RETURN Optional If the high count register rolls MOV 0FFh ERROR over set the ERROR register RETURN RTI Return to the main program SA...

Page 282: ...e resolution of the signal is 0 5 200 steps from 0 to 100 The T1 module is used in this example but T2n may be used in a similar manner for those devices which contain T2n Only the dimming function is covered in this application The SPI interface is illustrated in Using the TMS370 SPI and SCI Modules Application Report SPNA006 Figure 18 Display Dimming PWM Signal t1 t2 In this PWM application the ...

Page 283: ...he PWM pin is set either LO or HIGH If the new value is not 0 or 100 the T1 interrupt service routine is enabled and on the next interrupt the PWM duty cycle changes WhentheT1serviceroutineisentered theroutinestopsthePWMsignal loadsthenewvalues andrestarts Stopping the PWM signal helps avoid the possibility of inverting the signal if the new value is larger than the old for example when changing f...

Page 284: ...ontinue With Main Program Loop Does Duty Cycle 0 Set the T1PWM Pin Low Update the HI LO Duty Register Pair and Set the NEWVALUE Flag Continue With Main Program Loop Does Duty Cycle 100 Enable the T1 Compare Register to Cause an Interrupt Set the T1PWM Pin High T1 Interrupt Service Routine Begin T1 INT Service Routine Clear T1C Flag Stop T1 Load Upgrade Duty Cycle Information Reset T1 Reset T1PWM P...

Page 285: ...ile registers which are used in the routine T1CM EQU P042 T1C1 register MSB T1CL EQU P043 T1C1 register LSB T1CCM EQU P044 T1 compare compare 2 register MSB T1CCL EQU P045 T1 capture compare 2 register LSB T1PC1 EQU P04D T1 port control register 1 T1PC2 EQU P04E T1 port control register 2 T1CTL1 EQU P049 T1 control register 1 T1CTL2 EQU P04A T1 control register 2 T1CTL3 EQU P04B T1 control registe...

Page 286: ...alues of the MS LSDATA register pair against the HI LODUTY register pair If the values are different the PWM duty cycle needs to be changed The main loop also checks to see if any new value is between 0 and 100 If so the T1INT service is entered If the new value is 0 or 100 exactly the T1PWM pin is set to a general purpose output pin with the data value of 0 0 or 1 100 CHKSAME CMP MSDATA HIDUTY Ch...

Page 287: ...there has been a new value detected for the PWM duty cycle and that new value is not 0 0 or 4E20h 100 then clear the NEWVALUE flag and enable T1INT T1ENABLE SBIT0 NEWVALUE Clear the NEWVALUE flag MOV 01h T1CTL3 Allow the compare flag to cause a timer interrupt only when the PWM duty cycle needs to be altered Continue main routine BR MAIN This next section of code is only executed if the desired du...

Page 288: ...MOV 01100000b T1PC2 Reenable the T1PWM function with an initial value of 1 MOV 01110000b T1CTL4 Reenable the PWM toggling T1C and T1CC MOV 00h T1CTL1 Reselect the system clock as the T1 clock source The PWM signal now runs with the new duty cycle until the next change MOV 00000000b T1CTL3 Clear the T1 compare 1 interrupt flag and disable the T1 compare 1 flag again RETURN RTI Return to the main ro...

Page 289: ...the dimming and pulse width measurement requirements of a digital instrument cluster Certain calculation algorithms and subroutines are application specific and are left uncoded Additional information concerning the A D EEPROM and SPI modules may be found in this book A block diagram of the digital instrumentation example is shown in Figure 20 Figure 20 Digital Instrumentation Cluster Application ...

Page 290: ...ing of the display is controlled by reading an A D channel which is connected to a potentiometer This A D information is used to determine the duty cycle of a PWM signal output from T1 The information sent to the display is controlled using the SPI module The main routineinthisexamplecheckstoseethattheignitionswitchison Oncetheignitionswitchison thedisplay begins to be updated and a series of flag...

Page 291: ...utine Read New Dimming Potentiometer Value Restart A D for Next Read Return From Interrupt Begin T2n Interrupt Service Routine Did Overflow Flag Cause INT Clear TACH Flag Calculate the New Tachometer Values Update the Data Buffer With New Display Values Begin T1 Interrupt Service Routine Set the DELAY1 FLAG Every 10th Interrupt Has a New Duty Cycle Value Been Detected Output New T1PWM Signal Retur...

Page 292: ... the speed and tach input signals The module is set up for the dual cap ture mode to enable both 16 bit capture registers The T2nIC1 pin the T2n capture compare register and any T2n counter overflows are used to determine the speed function while the T2nIC2 pin the T2n capture register and any T2n counter overflows are used for the tach function When a valid signal occurs on either T2n input captu...

Page 293: ...00 s digit info ODO10 equ R10 Used to store the Odo s 10 s digit info ODO1 equ R11 Used to store the Odo s 1 s digit info ODOTENTH equ R12 Used to store the Odo s 1 10 s digit info FLAGS equ R13 Register used to store any software flags OVERCNT equ R14 Used to keep count of T2n overflows OVERSPD equ R15 Used for any T2n overflows during speed pulse OVERTACH equ R16 Used for any T2n overflows durin...

Page 294: ...A 10 Odometer 100 s digit DATA 11 Odometer 10 s digit DATA 12 Odometer 1 s digit DATA 13 Odometer 1 10 s digit DATA 14 Unused in this example DATA 15 DATA 16 DATA 17 DATA 18 DATA 19 DATA 20 NEWVALUE dbit 0 FLAGS Flag used to trigger a new PWM duty cycle IGNITION dbit 1 FLAGS Flag used to tell the main routine if the ignition switch is on or off DELAY1 dbit 2 FLAGS Flag used to signal a 1 10th seco...

Page 295: ...register LSB T2ACCM EQU P064 T2A capture 1 compare 2 register MSB T2ACCL EQU P065 T2A capture 1 compare 2 register LSB T2ACTL1 EQU P06A T2A control register 1 T2ACTL2 EQU P06B T2A control register 2 T2ACTL3 EQU P06C T2A control register 3 T2APC1 EQU P06D T2A port control 1 T2APC2 EQU P06E T2A port control 2 T2APRI EQU P06F T2A interrupt priority control SPICCR EQU P032 SPI configuration control re...

Page 296: ...ng at DATA 20 CLRREGS MOV A FLAGS 1 B DJNZ B CLRREGS Begin the module initialization routines T1INIT MOV 0C3h T1CM Set up the Tl compare register to contain MOV 04Fh T1CL C34Fh PWM frequency 100 Hz The actual frequency is not very important for this application Must load MSB first then LSB MOV HIDUTY T1CCM Load value for the duty cycle MOV LODUTY T1CCL Must load MSB first then LSB MOV 0 T1PC1 T1EV...

Page 297: ... SPICLK Baud rate CLKIN 8 MOV 00000110b SPICTL Master mode enable TALK ADINIT MOV 001h ADSTAT Enable interrupt clear flags MOV 0 ADPRI Select interrupt level 1 for the A D MOV 040h ADCTL Start sampling VSS3 selected as VREF AN0 selected as input channel MOV 0C0h ADCTL Start conversion EINT Enable interrupts The initialization block is completed Begin main program here Check to see if the ignition ...

Page 298: ...u can send a byte of data yet If so continue MOV DATA 1 B A Load the data to be sent out into MOV A SPIDAT the SPIDAT register DJNZ B CHKSPI Is the data string through yet MOV 025h SPIPC2 Toggle SPISOMI to latch data MOV 021h SPIPC2 Pull SPISOMI low again Check to see if a new A D reading has been taken If so check to see if this reading is different from the last reading CHKAD JBIT0 ADFLAG RETURN...

Page 299: ...h readings to the MOV TACH1 1 B A 4 registers in the data buffer set up MOV A DATA 1 B for the tach information used by DJNZ B LOADTACH the SPI RETURN BR MAIN Return to beginning Interrupt routines to follow The T1 interrupt service routine follows This routine is entered every 10 ms The duty cycle is altered only when the new data is loaded into the HIDUTY LODUTY register pair T1INT DJNZ MS50 CLE...

Page 300: ...alues into SPEEDMSB LSB register pair Must read LSB first MOV OVERCNT OVERSPD Save the contents of the OVERCNT register in OVERSPD Used in CALC routine SBIT1 SPDREAD Set the SPDREAD flag SPDRET RTI Read the capture register for the tach value CAPT2n MOV 10100110b T2ACTL2 Clear the flag and reenable the interrupt MOV T2ACL TACHLSB Read the capture register and store values MOV T2ACM TACHMSB into th...

Page 301: ...INT T2A vector word GOBACK SCI TX vector not used word GOBACK SCI RX vector not used word T1INT Timer 1 vector word GOBACK SPI vector not used word GOBACK INT 3 vector not used word GOBACK INT 2 vector not used word GOBACK INT 1 vector not used word START RESET vector end ...

Page 302: ...ftware and interface examples illustrate how the basic functions of the timer modules along with other modules of the TMS370 family can be used to providecost effectivesystemsolutions Thisapplicationreporthasbeendesignedtobeusedinconjunction with the TMS370 Family User s Guide The manual is a valuable reference and provides many answers to questions not addressed in this report ...

Page 303: ...gure 22 Timer 1 Dual Compare Mode T1C1 RST ENA 4C 4 4C 1 16 Bit Counter LSB MSB 41 40 16 Bit Compare Register LSB MSB 43 42 Prescaler Clock Source 16 Bit Capture Compare Register LSB MSB 45 44 T1C2 INT FLAG Flag 4B 1 INT ENA Compare 4B 6 T1C2 T1C1 INT FLAG Flag 4B 0 INT ENA 4B 5 T1C1 Compare Reset T1 OVRFL INT Flag 4A 4 T1 OVRFL INT ENA 4A 3 T1CR RST ENA T1 SW RESET 4A 0 T1 IC CR Pin Edge Select T...

Page 304: ... FLAG RC 0 T1 SW RESET S 0 Dual Compare Mode T1CTL3 104Bh P04B T1EDGE INT FLAG RC 0 T1C2 INT FLAG RC 0 T1C1 INT FLAG RC 0 T1EDGE INT ENA RW 0 T1C2 INT ENA RW 0 T1C1 INT ENA RW 0 Capture Compare Mode T1EDGE INT FLAG RC 0 T1C1 INT FLAG RC 0 T1EDGE INT ENA RW 0 T1C1 INT ENA RW 0 Dual Compare Mode T1CTL4 104Ch P04C T1 MODE 0 RW 0 T1C1 OUT ENA RW 0 T1C2 OUT ENA RW 0 T1C1 RST ENA RW 0 T1CR OUT ENA RW 0 ...

Page 305: ...NT FLAG 4B 0 4B 5 T1EDGE INT ENA Compare T1 OVRFL INT FLAG 4A 4 4A 3 T1EDGE INT ENA T1EDGE INT FLAG 4B 2 4B 7 T1EDGE INT ENA 16 Bit Compare Register LSB MSB 43 42 Edge Select SW RESET 4A 0 T1 IC CR Pin T1EDGE DET ENA 4C 0 TI EDGE POLARITY Reset T1C1 RST ENA 4C 4 T1C1 OUT ENA 4C 6 T O G G L E T1PWM PIN Level 1 INT 4F 6 Level 2 INT Flag Flag Flag 16 ...

Page 306: ...e peripheral file These registers are shown in Table 8 and are described in the TMS370 Family User s Guide The bits shown in the shaded boxes in Table 8 are privilege mode bits they can only be written to in the privilege mode Figure 24 and Figure 25 illustrate the T2A operational mode block diagrams ...

Page 307: ...NT FLAG RC 0 T2nC2 INT FLAG RC 0 T2nC1 INT FLAG RC 0 T2nEDGE 1 INT ENA RW 0 T2nC2 INT ENA RW 0 T2nC1 INT ENA RW 0 In Dual Capture Mode T2EDGE1 INT FLAG RC 0 T2EDGE2 INT FLAG RC 0 T2nC1 INT FLAG RC 0 T2nEDGE 1 INT ENA RW 0 T2nEDGE 2 INT ENA RW 0 T2nC1 INT ENA RW 0 In Dual Compare Mode T2nCTL3 106Ch 108Ch P06C P08 C T2n MODE 0 RW 0 T2nC1 OUT ENA RW 0 T2nC2 OUT ENA RW 0 T2nC1 RST ENA RW 0 T2nEDGE 1 O...

Page 308: ...B T2nEDGE1 OUT ENA T2nIC1 CR T2nEDGE1 POLARITY Toggle 16 bit compare MSB LSB register T2nCC 15 0 T2nC1 INT FLAG T2nCTL2 0 T2nCTL2 5 T2nC1 INT ENA T2nC2 INT FLAG T2nCTL2 6 T2nC2 INT ENA T2n OVRFL INT FLAG T2nCTL1 4 T2nCTL1 3 T2n OVRFL INT ENA T2nEDGE1 INT FLAG T2nCTL2 2 T2nCTL2 7 T2nEDGE1 INT ENA T2n PRIORITY T2nC2 OUT ENA T2nC1 OUT ENA T2nCTL3 6 T2nIC2 PWM T2nPC2 7 4 T2nPRI 6 T2nCNTR 15 0 T2nCTL1 ...

Page 309: ...ster 1 T2nC 15 0 16 bit compare MSB LSB register T2n PRIORITY Level 1 Int Level 2 Int 1 T2nCTL1 3 T2nCTL1 4 16 bit capture MSB LSB register 2 T2nIC 15 0 Edge 2 select T2nIC2 CR T2nPC2 7 4 T2nCTL3 1 Edge 1 select T2nIC1 CR T2nCTL3 2 T2nCTL3 0 16 T2nEDGE1 POLARITY T2nEDGE1 DET ENA T2nEDGE2 DET ENA T2nEDGE2 POLARITY T2nC1 INT FLAG T2nC1 INT ENA T2n OVRFL INT FLAG T2n OVRFL INT ENA T2nEDGE1 INT FLAG T...

Page 310: ...291 References Linear and Interface Circuits Applications SLYA003 Texas Instruments Incorporated 1987 TMS370 Family User s Guide SPNU127 Texas Instruments Incorporated 1996 ...

Page 311: ...ory has the capability to be programmed and erased under direct program control I interrupt AsignalinputtotheCPUtostoptheflowofaprogramandforcetheCPUtoexecuteinstructions at an address corresponding to the source of the interrupt When the interrupt is finished the CPU resumes execution at the point where the input occurred P PPM Pulse position modulation a serial signal in which the information is...

Page 312: ...le bit format to devices such as shift registers SYSCLK The internal system clock period W Watchdog timer A free running counter in the T1 module which must be cleared by the program at a set interval If the program is not working properly the counter will overflow causing a system reset ...

Page 313: ...294 ...

Page 314: ...295 Using Input Capture Pins as External Interrupts Michael S Stewart Microcontroller Products Semiconductor Group Texas Instruments ...

Page 315: ...296 ...

Page 316: ...NT flag to request an interrupt by setting the T1EDGE INT ENA T1CTL3 2 bit Timer 2A T2A The pins T2AIC1 CR and T2AIC2 PWM may be configured to operate as external interrupts To initialize the T2AIC1 CR pin to cause an external interrupt do the following 1 Select the mode of operation for T2A The T2A MODE T2ACTL3 7 bit can be selected for either dual compare mode or dual capture mode The T2AIC1 CR ...

Page 317: ... 0 bit 4 Enable the active T2BEDGE1 INT flag to request an interrupt by setting the T2BEDGE1 INT ENA T2BCTL3 2 bit To initialize the T2BIC2 PWM pin to cause an external interrupt do the following 1 Select the dual capture mode of operation for T2B The T2B MODE T2BCTL3 7 bit must be set The T2BIC2 PWM pin can operate as an external interrupt in the dual capture mode only In the dual compare mode th...

Page 318: ...299 Watchdog Design Considerations and Mask Options Michael S Stewart Microcontroller Products Semiconductor Group Texas Instruments ...

Page 319: ...300 ...

Page 320: ...d system reset The standard WD counter option is available on all ROM less mask ROM and some EPROM devices Mask ROM devices may be selected with the standard WD mask option by selecting the appropriate box in the device New Code Release Form NCRF EPROM devices that are represented with the A version designator TMS370C756A for example are designed with the standard WD counter All ROM less devices a...

Page 321: ...ss of the state of the INT1 individual interrupt enable and the global interrupt enable bits The hard WD counter option is available on all mask ROM and some EPROM devices Mask ROM devices may be selected with the hard WD mask option by selecting the appropriate box in the device NCRF EPROM devices represented with the B version designator for example TMS370C576B are designed with the standard WD ...

Page 322: ...See the TMS370 Family User s Guide for additional WD operational information The limited design of the TMS370 simple counter allows the counter to be used as an counter overflow interrupt The actual timebase of the overflow is dependent on SYSCLK speed tap select and clock prescale select This design does not allow a compare feature and limits the counter functionality ...

Page 323: ...304 ...

Page 324: ...305 T1PWM Set Up Routines Microcontroller Products Semiconductor Group Texas Instruments ...

Page 325: ...306 ...

Page 326: ... the T1PWM pin from a PWM pin to a general purpose output pin with a specific value The first instruction changes the pin to a general purpose output pin with the same value as the current PWM pin The second instruction changes the pin to a particular value MOV 50h P04E Stop with PWM pin high MOV 50h P04E MOV 10h P04E Stop with PWM pin low MOV 10h P04E Routine 3 This routine starts and stops the P...

Page 327: ...308 ...

Page 328: ... III Module Specific Application Design Aids Part III contains six sections RESET Operations 99 SPI and SCI Modules 105 Timer and Watchdog Modules 199 Analog to Digital Modules 309 PACT Module 375 I O Pins 439 ...

Page 329: ...310 ...

Page 330: ...311 Using the TMS370 ADC1 Module Henry Kwan Microcontroller Products Semiconductor Group Texas Instruments ...

Page 331: ...312 ...

Page 332: ...volve the determination of the values of physical parameters such as temperature position and pressure that must be transformed into electrical analog signals and then converted to digital codes for the controller With the on chip ADC1 the TMS370 microcontrollers greatly simplify interactions between the analog world and a digital system This application report illustrates the operation of the ADC...

Page 333: ...N2 ADENA 3 ADIN 3 Port E input ENA 3 Port E data AN 3 AN3 ADENA 4 ADIN 4 Port E input ENA 4 Port E data AN 4 AN4 ADENA 5 ADIN 5 Port E input ENA 5 Port E data AN 5 AN5 ADENA 6 ADIN 6 Port E input ENA 6 Port E data AN 6 AN6 ADENA 7 ADIN 7 Port E in put ENA 7 Port E data AN 7 AN7 VCC3 VSS3 ADCTL 6 Sample start ADCTL 7 Convert start ADDATA 7 0 ADC data register ADSTAT 2 AD ready AD priority ADPRI 6 0...

Page 334: ...nce called the sample mode the analog input is sampled by connecting VIN to the analog input and closing switch Sc and all St switches All capacitors charge up to the input voltage simultaneously during the sampling time Capacitor Co is switched to VREF during sample mode In the second sequence the hold mode capacitor Co is switched to GND switch Sc is opened and VIN is connected to GND In the thi...

Page 335: ...ted the SAMPLE START and the CONVERT START bit bit 7 of the ADCTL are set The analog signal s value will be held by the ADC1 module for 18 cycles after the CONVERT START bit is set By that time the ADC1 module has cleared both the SAMPLE START and CONVERT START bit to signify the end of the internal sampling phase After the internal sampling phase the program can change the input channel without a...

Page 336: ...filtering can be accomplished by adding a resistor and capacitor across the ADC1 inputs as shown in Figure 5 and Figure 6 For inexpensive filtering CX acts with RX to form a first order low pass network However the capacitor and resistor size should be chosen carefully to preclude additional system errors One of the most common A D application errors is inappropriate source impedance Too much sour...

Page 337: ...in from damage Also the internal diode to VCC 5 V would clamp the voltage at node A see Figure 3 at 5 7 V Let X be the resistance of the external resistor Therefore 12 7 12 5 7 X 900 X or X 3 46 k It is suggested that the designer add in some guard band for tolerance of the internal resistance and fluctuationsof the external power supplies The designer may also consider using external clamping dio...

Page 338: ...ejection Infinity Bandwidth Frequency response of the op amp Infinity Op amps can be configured to perform a large number of functions Because of their variable characteristics and wide range of adaptability they are very handy for analog signal interfacing Two popular input buffer configurations for the op amp are shown in Figure 5 and Figure 6 The noninverting configuration provides amplificatio...

Page 339: ... signals to the ADC1 converter Figure 7 Range Offsetting and Scaling 2 5 V VOLTAGE REFERENCE 2R VO 0 V 5 V R TRANSDUCER R2 2 5 V 12 5 V The bridge amplifier is another very popular interfacing circuit especially applicable with input transducers Transducers like strain gauges and thermistors simply produce a varying resistance over a range of parameter pressure or temperature changes Figure 8 show...

Page 340: ... an input buffer to the ADC1 converter A current amplifier can provide current to a voltage converter A low pass filter can reduce system noise to achieve a better A D conversion accuracy Alogarithmicampcancompresstheinputsignalfromseveralordersofmagnitudetoanonlinear input signal with a fixed percent of relative accuracy throughout the required range For more information refer to linear circuits ...

Page 341: ...t digital output with the MSB bit 8 the extra bit equal to 0 The output of channel AN1 will be zero because of the offset When the input signal is within the range 2 5 to 5 V channel AN1 provides the conversion result 8 bit digital output with the MSB bit 8 the extra bit equal to 1 The output of channel AN0 will be FF its full scale value The user should note that when the input signal is within t...

Page 342: ...output Theintegralofthepseudorandomnoiseiszero over a long period of time When the pseudo noise is injected the conversion result varies by some number of LSBs from a nominal value see Figure 11 The final average value depends on where the original input signal lies within the code width of the converter If the input signal is not at the center of a code the computed average will show either a neg...

Page 343: ...other words the absolute value of the analog input is of no particular concern but the ratio of the output to the full scale value is important The analog reference maximum of the input signal can be one of the analog input channels AN1 to AN7 This allows maximum full scale utilization of the ADC1 converter However the absolute accuracy of the ADC1 converter is tested at VREF equal to 5 1 V The ab...

Page 344: ...eanalogsource impedance is less than or equal to 1 kilohm for minimum sampling time the sampling time is limited by the instruction cycle time to set up the SAMPLE START bit the minimum sampling time is 1 6 µs using a 5 MHz SYSCLK In that case the ADC1 can convert an analog input in every 34 4 µs for a maximum conversion rate of 29 069 conversions per second To meet the Nyquist criterion the maxim...

Page 345: ...grounds should be run separately from the digital ground line to make sure that there are no common impedance earth paths with digital ground or other circuits as shown in Figure 14 and Figure 15 Analog ground should be connected to a low impedance point near the power supply During the conversion current flow into the analog ground can be changed with a high impedance in the ground line Such chan...

Page 346: ...he absolute error in term of the LSB may increase The source impedance ZREF of VREF Figure 16 should not exceed the value specified in the electrical specification 24 kΩ for SYSCLK less than 3 MHz and 10 kΩ for SYSCLK higher than 3 MHz During the conversion process the reference voltage charges and discharges the capacitor array to determine the conversion value If the reference voltage source imp...

Page 347: ...ecently converted result The channel assignments for this program are Analog input channel AN0 Ref channel VCC3 Figure 17 APNTR Pointer ATABLE APNTR OLDEST MOST RECENTLY CONVERTED RESULT We have shown that the maximum sampling frequency is limited by the conversion rate of the ADC1 and the Nyquist criterion With a SYSCLK of 5 MHz the maximum conversion rate is 29 069 conversions per second or the ...

Page 348: ...NIT0 MOV A ATABLE 1 B CLEAR ALL EIGHT BYTES DJNZ B INIT0 The following section sets up the on chip timer to control the sampling frequency The conversion period is loaded into the timer compare register T1C When the counter T1CNTR matches the T1C an interrupt request will be generated The timer interrupt service routine will initiate an A D conversion and set up the time for the next conversion in...

Page 349: ...ART CONVERSION RTI The following section is the ADC1 interrupt routine It saves the conversion results in the ATABLE and setsthe pointer to the next available location The address of the label ATOD must be placed in the interrupt vector table located at 7FECh and 7FEDh INTERRUPT ROUTINE FOR ADC1 ADFLAG DBIT 1 ADSTAT NAMED THE INTERRUPT FLAG AS ADFLAG ATOD PUSH A SAVE THE REGISTERS PUSH B SBIT0 ADF...

Page 350: ...ADC1 interrupt routine as a signal to the main program that all four channels have been processed The address of the label ATOD must be placed into the interrupt vector table located at 7FECh and 7FEDh Table 2 Analog Input Table Analog Input Channel Ref Channel AN3 AN7 AN2 AN6 AN1 AN5 AN0 AN4 Routine REG ADCHANL KEEP CURRENT CHANNEL NUMBER REG ATABLE 4 4 BYTE TABLE THAT STORES CHANNEL DATA INIT MO...

Page 351: ...DSTAT ENABLE THE INTERRUPT AND CLEAR ANY FLAGS MOV 07BH ADCTL START SAMPLING APPROX 2uS DELAY FOR CLOCKIN 20 MHZ MOV 0FBH ADCTL START CONVERSION RTS The following section is the ADC1 interrupt routine It saves the conversion result in the ATABLE and initiates another conversion If it does not all four channels have already been processed INTERRUPT ROUTINE FOR ADC1 ATOD PUSH A SAVE THE REGISTERS PU...

Page 352: ...onversion that is using multiple input and reference sources The routines can be easily extended to multiple channel conversions with the on chip timer controlling the sampling frequency In some cases the user may even want different sampling frequencies for different channels to account for any disparity in the frequencies of the input signals One way to achieve this is to set the time base outpu...

Page 353: ...g gain offset drift over time and tolerance problems that can affect system accuracy Alternatives such as table lookup techniques or linearization algorithms might reduce the need for expensive hardware linearization The values of physical parameters can be calculated beforehand and stored in a table Upon conversion completion theapplicationsoftwarewillsimplyretrievethevalueoftheparameterbyusingth...

Page 354: ...SULT MOV ATPNT B SWAP B GET THE INDEX FIELD RL B AND 1FH B GET THE VALUE FROM THE TABLE MOV ATABLE B A GET F I MOV A RESULT CHECK IF INTERPOLATION NECESSARY IF THE MOST LEAST SIGNIFICANT THREE BITS ARE ZERO NO INTERPOLATION IS NECESSARY BTJO 07H ATPNT INTERP JMP FINISH INTERP INC B SET INDEX POINT TO NEXT ENTRY MOV ATABLE B A GET F I 1 SUB RESULT A CALCULATE THE DIFFERENCE F I 1 F I AND 07H ATPNT ...

Page 355: ...ith the on chip EEPROM capability the translation table can be adjusted for correction as environmental conditions change Also the write protection feature of the data EEPROM can be used to protect the translation table from inadvertent overwriting by the application software For more detailed information about the on chip data EEPROM refer to the TMS370 Family User s Guide ...

Page 356: ... 2K7 RF 100kW RS2 VT 470W 470W 1kW TLC272 VO RX RP 47kW 0 1 µF CX VCC3 AN0 TMS370 I O I O 4 7 µF 1K 1kW The bridge is comprised of resistors R1 R2 R3 and a temperature sensor either RS1 or RS2 The differential output voltage of the bridge is forced to zero by the feedback connection The circuit is configured as a current amplifier Potentiometer P1 and resistor R4 are used to adjust any offset pres...

Page 357: ...hanging the amplification resistance at the noninverting terminal of the noninverting amplifier TLC272 The actual gain of the amplifier is greatly dependent on the accuracy of the resistors Usually additional variable resistors are used to adjust the gain of the amplifier However if the exact gain of the amplifier at each range is calibrated and stored in the data EEPROM these manual adjustments c...

Page 358: ...cuit Diagram VIN 3 2 VCC3 8 1 4 TLC272 68 kΩ VCC3 30 kΩ 15 kΩ VCC3 10 kΩ 23 LM399 LM399 10 kΩ VCC3 17 24 5 4 3 2 12 370Cx5x AN6 DIGITAL I O AN0 AN7 DIGITAL I O 51 50 INT2 INT3 DIGITAL I O DIGITAL I O 9 8 14 30 kΩ 10 kΩ VCC3 10 kΩ 20 kΩ 68 kΩ TLC4066 TLC4066 TLC4066 2 3 9 B B B C R T L C R T L C R T L A A A 13 5 4 2 6 6 6 4 8 4 5 7 1 3 5 74LS04 74LS04 74LS04 74LS139 1 3 2 Y0 Y1 Y2 Y3 A B G 1 ...

Page 359: ... REGISTER G1 DBIT 3 INT2 GAIN FACTOR CONTROL BIT 1 INT3 EQU P019 INT3 PIN CONTROL REGISTER G0 DBIT 3 INT3 GAIN FACTOR CONTROL BIT 0 REG RESERVE 10 RESULT 1 INDICATE THE INPUT SIGNAL RANGE GAIN FACTOR RESULT CONVERSION RESULT REGPAIR RESULT 16 BIT REGISTER FOR CONVERSION RESULT REGPAIR GAIN TEMP REG TEXT 7000H INIT MOV 0FEH ADENA ENABLE ANO AS ANALOG CHANNELS AN1 AN7 AS GENERAL PURPOSE INPUT PINS M...

Page 360: ...ng section is the subroutine to initiate the A D conversion The subroutine first reads the output of the comparators via AN6 and AN7 to determine the input voltage range If the input signal is within the desired range then an A D conversion will be initiated Otherwise the subroutine will adjust the gain factor and repeat the process one more time SUBROUTINE SECTION SAMPLE PUSH A UPPER MOV ADIN A B...

Page 361: ...us UNTIL THE OP AMP IS STABLE JMP UPPER CONVRT MOV 01H ADSTAT ENABLE THE INTERRUPT AND CLEAR ANY FLAGS MOV 040H ADCTL START SAMPLING APPROX 2µS DELAY FOR CLOCKIN 20 MHZ MOV 0C0H ADCTL START CONVERSION POP A RTS The following section is the ADC1 interrupt routine It saves the conversion result in the register RESULT INTERRUPT ROUTINE FOR ADC1 ATOD MOV 01 ADSTAT CLEAR THE INTERRUPT FLAG MOV ADDATA R...

Page 362: ...ram of the interface between TLC1540 1 and TMS370 This section describes the interface of a 10 bit serial A D converter through the SPI The system clock of the TLC1540 1 is provided by the CLKOUT pin of the TMS370 Note that the maximum TLC1540 1 system clock frequency is only 2 1 MHz an additional frequency divider counter may required if the SYSCLK frequency is higher than 2 1 MHz The serial A D ...

Page 363: ...he flag CNVCMPL is set by the SPI routine as a signal to the main program that all 11 channels have been processed The address label SPIINT must be placed in the interrupt vector table located at 7FF6h and 7FF7h Data Conversion Routine SPISIMO SPI FUNCTIONAL PIN CONNECT TO TLC1540 1 ADDRESS INPUT SPISOMI SPI FUNCTIONAL PIN CONNECT TO TLC1540 1 DATA OUTPUT SPICLK SPI FUNCTIONAL PIN CONNECT TO TLC15...

Page 364: ... the TMS370 Family User s Guide SET UP SPI CONFIGURATION INIT MOV 087H SPICCR INITIALIZES SPI CIRCUITRY SELECT CLOCK POLARITY INACTIVE LOW SELECT BIT RATE CLKIN 8 SELECT CHARACTER LENGTH 8 MOV 07H SPICTL CONFIGURE AS MASTER TRANSMISSION ENABLE TALK 1 INTERRUPT ENABLE MOV 02H SPIPC1 SET SPICLK AS FUNCTION PIN MOV 22H SPIPC2 SET SPISOMI AND SPISIMO AS FUNCTION PIN MOV 20H SPIPRI SET EMULATOR SUSPEND...

Page 365: ... is completed an interrupt request will be generated Subsequent transmissions will be driven by the interrupt routine SUBROUTINE SECTION RESTART CLR ADCHANL INITIALIZE CHANNEL ADDRESS CLR FLAGS CLEAR ALL FLAGS MOV 01H SPICCR SET CHARACTER LENGTH TO 2 MOV 10H INT3 ACTIVATE TLC1540 1 CHIP SELECT MOV 00H SPIDAT TRANSMIT THE CHANNEL ADDR RTS The following section is the SPI interrupt routine It saves ...

Page 366: ...ROM FROM PREVIOUS TRANSMISSION THEY ARE THE LEAST 2 SIGNIFICANT BITS OF THE CHANNEL ADDRESS TRAN8 MOV A SPIDAT INITIATE TRANSMISSION AND 03H A GET THE LAST 2 BITS ONLY MOV A ATABLE 1 B STORE THE MOST SIGNIFICANT 2 BITS NOST INC FLAGS SET THE FLAG INDICATE THE LSB RESULT ALREADY RECEIVED JMP EXITSP CMPLT MOV A ATABLE B STORE THE LEAST SIGNIFICANT 8 BITS NOST1 CMP 0BH ADCHANL CHECK IF ALL CONVERSION...

Page 367: ...INITIATE ANOTHER TRANSMISSION CLR FLAGS CLEAR THE FLAG INDICATE THE CHANNEL ADDRESS ALREADY TRANSMITTED EXITSP POP B RESTORE THE REGISTERS POP A EXIT RTI INIT INTERRUPT VECTORS SECT vect 7FECH WORD 0 0 0 0 0 SPIINT 0 0 0 INIT ...

Page 368: ...ort without any additionalhardware Itconvertsdatafromall11channelsandstoresthedigitalresultsintoatablebeginning at ATABLE The table contains 11 16 bit registers The least significant byte is located at the lowest address The routine stops interrupting the main program after it finishes all 11 channels If the main program wants more recent data it needs only to execute the code at CONVRT Figure 22 ...

Page 369: ...U P02D DPORT 2 CLKOUT CONFIGURATION REG DDATA EQU P02E DPORT DATA REG DDIR EQU P02F DPORT DATA DIR REG INT1 EQU P017 INT1 PIN CONTROL REGISTER INT2 EQU P018 INT2 PIN CONTROL REGISTER INT3 EQU P019 INT3 PIN CONTROL REGISTER REG RESERVE 10 REG ATABLE 22 16 BIT REGISTERS FOR CONVERSION RESULT REGPAIR RESULT 2 TEMPORARY RESULT REGISTER REG FLAG REG FLAG REG ADCHANL REG BITCNT REG CHNLCNT IOCLK DBIT 3 ...

Page 370: ...URPOSE I O MOV 00H DPORT2 MOV 08H DDIR MOV 0A0H B LDSP INITIALIZE STACK POINTER TO 0A0H CLR A MOV 22 B AGAIN MOV A ATABLE 1 B INITIALIZE THE TABLE DJNZ B AGAIN EINT ENABLE INTERRUPT LOOP CALL CONVRT START CONVERSIONS MAIN PROGRAM GOES HERE NEED MORE RECENT DATA NOP CALL CONVRT START TAKING MORE DATA NOP MORE MAIN PROGRAM ...

Page 371: ...CHANL INITIALIZE CHANNEL ADDRESS THE UPPER 4 BITS INDICATE THE CHANNEL ADDRESS CLR FLAG CLEAR ALL FLAGS MOV 12 CHNLCNT SET COUNT TO NUMBER OF CHANNELS 1 ONE MORE TRANSMISSION TO READ BACK THE CONVERSION RESULT NEXT MOV ADCHANL B SWAP B PASS THE CHANNEL ADDRESS TO SUBROUTINE THROUGH REGISTER B THE UPPER 4 BITS IS THE CHANNEL ADDRESS CLR RESULT CLEAR THE TEMPORARY REGISTER CLR RESULT 1 CALL ADTRAN T...

Page 372: ...OM TLC1540 ENTER B AD CHANNEL ADDRESS UPPER 4 BITS EXIT RESULT 10 BIT RESULT ADTRAN SBIT0 CS CHIP SELECT ACTIVE SBIT1 IOCLK SEND TWO CLOCK PULSES TO TLC1540 SBIT0 IOCLK SBIT1 IOCLK SBIT0 IOCLK MOV 8 BITCNT SET UP COUNTER ADRTRA SBIT1 ADADDR TRANSMIT THE ADDRESS RL B JC BIT1 IS ADDRESS EQUAL TO 1 SBIT0 ADADDR NO SET IT BACK TO 0 BIT1 SBIT1 IOCLK RLC RESULT GET THE CONVERTED RESULT RLC RESULT 1 THE ...

Page 373: ...S MUST BE DEACTIVATED TWO I O CLOCK BEFORE THE END OF TRANSMISSION JMP BIT1 DONE RTS INIT INTERRUPT VECTORS SECT vect 7FFEH WORD BEGIN The above examples demonstrate the basic principle of interfacing a serial A D with the TMS370 family microcontrollers ForapplicationsthatuseTMS370x10 butonlyneedonechannelA D youmayconsider TLC548 9 which is a single channel 8 bit A D converter ...

Page 374: ...the operation of the ADC1 typical methods of interfacing to the external circuits and interactions with other modules The TMS370 on chip timer provides a handy method to control the sampling frequency of conversions Calibration data of analog components can be stored in the data EEPROM module This data can be used to adjust the conversion result to achieve high system accuracy while using inexpens...

Page 375: ...ode Figure 23 ADC1 Control Register Memory Map BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 CONVERT START SAMPLE START REF VOLT SELECT 2 AD INT ENA RESERVED PORT E DATA INPUT REGISTER AD STEST AD PRIORITY AD ESPEN ADDR PF 1070h 070 1071h 071 1073h 073 to to 107Ch 07C 107Dh 07D 107Eh 07E ADSTAT 1072h 072 A TO D CONVERSION DATA REGISTER PORT E INPUT ENABLE REGISTER 107Fh 07F ADCTL ADDATA ADIN ADE...

Page 376: ...rror gain error linearity error and is generally expressed in terms of LSB The absolute error denoted by a is 1 LSB differential linearity error The difference between the actual step width and the ideal value If the differential linearity error is greater than 1 LSB this can lead to missing codes in the A D conversion nonmonotonicity The absolute error denoted by b is 1 2 LSB gain error The diffe...

Page 377: ...on chip A D can provide For applications requiring high accuracy but slow conversion rate in ms one can use a dual slope A D converter like TL505C The on chip timer can be used to generate precise timing control signals and measure the output timing input capture function to determine the input voltage Figure 25 Functional Block Diagram of TL505C Interface With TMS370 INTEG RES INTEG IN INTEG IN T...

Page 378: ...ure 26 Conversion Timing Diagram VO ofs V1 V2 V3 A B INTEGRATOR OUTPUT COMPARATOR OUTPUT t0 t1 t2 t0 V1 V2 V3 VI VO ofs CONTROL ANALOG A B SWITCHES CLOSED L L S1 S2 H H S3 L H S1 S4 VIN VREF t2 t1 H VIH L VIL ...

Page 379: ...ne the input voltage The TMS370 performs a binary search to determine the digital value of the input voltage 10 conversions for 10 bit D A converter Figure 27 Functional Block Diagram Using D A Converter as A D UP DOWN OUT1 OUT2 GND BIT1 BIT10 TLC7533 D A CONVERTER RFB REF DATA IN CLK SHIFT REGISTER COMPARATOR DIGITAL INPUT D THRESHOLD VREF D 1024 VIN VREF SPISIMO SPICLK TMS370 I O ...

Page 380: ...ate frequency outputs up to 500 kHz The on chip timer can provide precise timing measurements for the frequency output signal For a clock frequency of 5 MHz the timer clock period is 200 ns the accuracy of the A D conversion will mainly depend on the V F converter Figure 28 Functional Block Diagram Using V F Converter as A D AD654 V F CONVERTER T1IC CR FOUT Rt TMS370 VCC R C INPUT VIN FOUT VIN 10R...

Page 381: ...ction provides information about testing two A D converter parameters absolute accuracy and differential linearity error Table 4 Test Conditions SYSCLK 0 5 MHz and 5 MHz VCC3 5 5 V Vref 5 1 V Sampling time 2 µs SYSCLK 5 MHz 20 µs SYSCLK 0 5 MHz ...

Page 382: ... are used to provide accurate reference voltage and an analog input signal At the theoretical midpoint of each code 256 conversions are performed If all 256 digital codes are generated by these conversions this guarantees that the A D conversions are within one LSB absolute accuracy The differential linearity error is measured by the code width or voltage range of each individual code WithVref at5...

Page 383: ...sions is performed with input decremented at a step of 2 mV starting from the midpoint of 80 The analog voltage 80min is the minimum possible value before any conversion that generates 7F In order to minimize the test time for the ADC1 modules only 14 codes are tested for the differential linearity error see Figure 31 These 14 codes have the largest differential linearity errors In the Module Desc...

Page 384: ...00 0111 0000 1111 0000 1000 0001 0000 0001 1111 0000 1111 0010 0000 0100 0000 0111 1111 1000 0000 Figure 32 Differential Linearity Error CONVERTED DIGITAL CODE TMX37050 TEMPERATURE 25 C FREQUENCY 2MHz DISTANCE FROM MID POINT mV 25 20 15 10 5 0 5 10 15 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 ...

Page 385: ... to be sampled to recover the original signal without distortion ratiometric conversion The output of an A D conversion which is a digital number proportional to the ratio of the input to a fixed or variable reference In some applications where the measurement is affected by the slow varying changes of the reference voltage comparable to the conversion time it is advantageous to use that same refe...

Page 386: ...State Circuits 1975 Pippenger D E and Tobaben E J Linear and Interface Circuits Applications Texas Instruments Technical Publishing Dallas Texas 1986 Sheingold Daniel H Transducer Interface Handbook Analog Devices Inc Massachusetts 1981 The Handbook of Linear IC Applications Burr Brown Corporation Tucson Arizona 1987 T I Microcontroller Applications Group TMS370 Family User s Guide Texas Instrumen...

Page 387: ...368 ...

Page 388: ...369 Analog to Digital A D Helpful Hints Michael S Stewart Microcontroller Products Semiconductor Group Texas Instruments ...

Page 389: ...370 ...

Page 390: ...A D module voltage reference selection allows various voltages or input signals to be used as reference voltages for other analog input signals See Chapter 11 of the TMS370 Family User s Guide for additional information A D Source Impedence The TMS370 A D module incorporates a successive approximation design for the conversion circuitry To guarantee the internal circuitry is allowed to charge suff...

Page 391: ...edance of AN5 5 kΩ The result of the conversion will be polled interrupt driven routines are similar SYSCLK 5 MHz Code ADCTL EQU P070 A D equates ADSTAT EQU P071 ADDATA EQU P072 ADIN EQU P07D ADENA EQU P07E ADPRI EQU P07F AD_READY DBIT 2 ADSTAT Bit definitions AD_FLAG DBIT 1 ADSTAT REG BUFFER Define a register START MOV 0DFh ADENA Make sure AN5 can be selected an analog input All others may be dig...

Page 392: ...373 WAIT JBIT0 AD_FLAG WAIT Wait on the AD INT FLAG bit to be set MOV ADDATA A Read conversion data store in BUFFER MOV A BUFFER ...

Page 393: ...374 ...

Page 394: ... III Module Specific Application Design Aids Part III contains six sections RESET Operations 99 SPI and SCI Modules 105 Timer and Watchdog Modules 199 Analog to Digital Modules 309 PACT Module 375 I O Pins 439 ...

Page 395: ...376 ...

Page 396: ...377 PACT Command Macros Microcontroller Products Semiconductor Group Texas Instruments ...

Page 397: ...378 ...

Page 398: ... Interrupt on compare int_evt1 EQU 2 x Interrupt on event 1 int_trst EQU 4 x x Interrupt on timer 0 enable EQU 8 x x x x Enable timer or pin rst_def_tmr EQU 10h x Reset def tmr on evt max rst_def_ev2 EQU 10h x Reset def tmr on evt 2 set_pin EQU 20h x x Set output pin on set_evt1 EQU 20h x Set output pin on evt1 step EQU 40h x x x Go to half resolution int_evt EQU 80h x Interrupt on each event int_...

Page 399: ...time compare value 16 bit value compared to the reffered timer pin Output pin only pin 1 7 are valid possible actions nxt_def int_cmp set_pin clr_pin evt_plus1 register label a symbol to be equated to the register containing the least significant byte of this command CONCMP MACRO evcmpval cmpval pin actions lab var b1 b2 b3 b4 if cmpval v 0 cmpval v 1 ERROR compare value must be greater than 1 end...

Page 400: ...al v b2 v if pin v 1 pin v 8 asg 1 pin v ERROR pin selection is illegal endif asg pin v 1 pin v if actions v 09984h 0 ERROR illegal action specified endif asg actions v 063h pin v 2 b3 v asg actions v 18h actions v 8 66h 1 b4 v byte b1 v b2 v b3 v b4 v if lab l 0 asg cmd_st table 4 b1 v lab equ r b1 v endif ENDM VIRTUAL TIMER DEFINITION virtmr period actions initial timer value register label peri...

Page 401: ...lue 16 bit virtual timer initial value possible actions rx tx register label a symbol to be equated to the register containing the least significant byte of this definition BRTMR MACRO maxcount actions tmrval lab var b1 b2 b3 b4 if actions v 0E7FFh 0 ERROR illegal action specified endif asg tmrval v 0FEh b1 v asg tmrval v 8 0FFh b2 v if maxcount v 8 0FFh 1Fh asg maxcount v 9 70h maxcount v 3 80h 0...

Page 402: ...ter containing the least significant byte of this definition OFSTMR MACRO maxcount actions tmrval lab var b1 b2 b3 b4 if maxcount v 255 maxcount v 0 ERROR Maximum event value out of range endif if actions v 09E27h 0 ERROR illegal action specified endif asg tmrval v 0FFh 1 b1 v asg tmrval v 8 0FFh b2 v asg actions v 090h actions v 8 1 actions v 40h 6 b3 v asg b3 v actions v 100h 7 actions v 8 60h b...

Page 403: ...384 ...

Page 404: ...385 PACT Module Sample Routines J L Pettegola Microcontroller Products Semiconductor Group Texas Instruments ...

Page 405: ...386 ...

Page 406: ...s throughout this report PACTSCR EQU P040 setup control register CDSTART EQU P041 CMD DEF area start register CDEND EQU P042 CMD DEF area end register BUFPTR EQU P043 buffer pointer register DUMMY EQU P044 unused register SCICTLP EQU P045 PACT SCI control register RXBUFP EQU P046 PACT SCI receive data register TXBUFP EQU P047 PACT SCI transmit data register OPSTATE EQU P048 output pin 1 to 8 state...

Page 407: ...um divide rate for the prescaled clock can be derived Set and reset the PWM output No timer definition is required for the default timer so only two standard compares will be needed Since there are no captures no capture register or circular buffer is required Define the size of the command and definition area and set the start and end address in the dual port RAM 1 TS NEEDED FREQUENCY MAX SYSCLK ...

Page 408: ... DEFAULT TIMER CMD DEF 2 STANDARD COMPARE COMMAND ON DEFAULT TIMER 1 TS COMPARE VALUE 0000H RESET OP1 ON COMPARE 8000H ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Reserved ÁÁÁ ÁÁÁ ÁÁÁ EN ÁÁ ÁÁ ÁÁ IR ÁÁÁ ÁÁÁ ÁÁÁ RA ÁÁÁ ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ ÁÁÁ ST ÁÁÁ ÁÁÁ ÁÁÁ CA ÁÁÁ ÁÁÁ ÁÁÁ Pin Select ÁÁÁ ÁÁÁ ÁÁÁ IC ÁÁÁ ÁÁÁ ÁÁÁ NX ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Timer Compare Value ÁÁ ÁÁ 0ÁÁ ÁÁ 0ÁÁ ÁÁ 0 ÁÁ ÁÁ 0 ÁÁÁ ÁÁÁ 1 ÁÁ ÁÁ 0ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁ...

Page 409: ...trol register ENDAD EQU 01E8H INIT PACT PERIPHERAL FRAME OR 003H PACTPRI DISABLE WATCHDOG MODE A MOV STARTAD 0100H 080H CDSTART START AD CMD DEF INT DIS MOV ENDAD 0100H CDEND END AD MOV 010H PACTSCR SYSCLK DIVIDED BY 2 RESOL 400NS AT 20MHZ MAIN PGM MAIN OR 020H PACTSCR ENABLE PACT CMD DEF AREA JMP LOOP MAIN PGM INIT PACT CMD DEF AREA sect CMDEF ENDAD CMD DEF SECTION PROGRAM WORD 0800H 0000H RESET ...

Page 410: ...Á ÁÁ 0ÁÁ ÁÁ 0ÁÁ ÁÁ 0 ÁÁ ÁÁ 0 ÁÁÁ ÁÁÁ 1 ÁÁ ÁÁ 0ÁÁÁ ÁÁÁ 1 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁ ÁÁ 0 Á Á 0 ÁÁ ÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁÁÁ ÁÁÁÁÁ 8000h ÁÁÁÁÁ ÁÁÁÁÁ D31 D28 ÁÁÁ ÁÁÁ D27 ÁÁ ÁÁ D26 ÁÁÁ ÁÁÁ D25 ÁÁÁ ÁÁÁ D24ÁÁÁ ÁÁÁ D23 ÁÁÁ ÁÁÁ D22 ÁÁÁ ÁÁÁ D21 ÁÁÁ ÁÁÁ D20 D18 ÁÁÁ ÁÁÁ D17 ÁÁÁ ÁÁÁ D16 ÁÁÁÁÁ ÁÁÁÁÁ D15 D0 WORD 00A00H 08000H RESET OP1 ON 08000h DEFAULT TIMER SET ON ZERO CMD DEF 2 STANDARD ...

Page 411: ...2 ÁÁÁ D21 ÁÁÁ D20 D18 ÁÁÁ D17 ÁÁÁ D16 ÁÁÁÁÁ D15 D0 WORD 00828H 04000H SET OP3 ON 04000h DEFAULT TIMER CMD DEF 4 STANDARD COMPARE COMMAND ON DEFAULT TIMER 1 TS COMPARE VALUE 0C000H DUTY CYCLE 50 RESET OP3 ON COMPARE ÁÁÁÁÁ ÁÁÁÁÁ Reserved ÁÁÁ ÁÁÁ EN ÁÁ ÁÁ IR ÁÁÁ ÁÁÁ RA ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ ST ÁÁÁ ÁÁÁ CA ÁÁÁ ÁÁÁ Pin Select ÁÁÁ ÁÁÁ ICÁÁÁ ÁÁÁ NX ÁÁÁÁÁ ÁÁÁÁÁ Timer Compare Value ÁÁ ÁÁ 0ÁÁ ÁÁ 0ÁÁ ÁÁ...

Page 412: ... FRAME DEBUT OR 003H PACTPRI DISABLE WATCHDOG MODE A MOV STARTAD 0100H 080H CDSTART START AD CMD DEF INT DIS MOV ENDAD 0100H CDEND END AD MOV 014H PACTSCR SYSCLK DIVIDED BY 5 RESOL 1µS AT 20MHz MAIN PGM MAIN OR 020H PACTSCR ENABLE PACT CMD DEF AREA JMP LOOP MAIN PGM INIT PACT CMD DEF AREA sect CMDEF ENDAD CMD DEF SECTION PROGRAM WORD 00808H 0C000H RESET OP3 ON 0C000h DEFAULT TIMER ERO WORD 00828H ...

Page 413: ...D AS A TIMER DEFINITION ÁÁÁÁÁ ÁÁÁÁÁ Reserved ÁÁÁ ÁÁÁ EN ÁÁ ÁÁ IR ÁÁÁ ÁÁÁ RA ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ ST ÁÁÁ ÁÁÁ CA ÁÁÁ ÁÁÁ Pin Select ÁÁÁ ÁÁÁ IC ÁÁÁ ÁÁÁ NX ÁÁÁÁÁ ÁÁÁÁÁ Timer Compare Value ÁÁ ÁÁ 0 ÁÁ ÁÁ 0 ÁÁ ÁÁ 0 ÁÁ ÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁ ÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁ ÁÁ 0 Á Á 0 ÁÁ ÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 1 ÁÁÁÁÁ ÁÁÁÁÁ 0000h ÁÁÁÁÁ ÁÁÁÁÁ D31 D28 ÁÁÁ ÁÁÁ D27 ÁÁ ÁÁ D26 ÁÁÁ ÁÁÁ...

Page 414: ...irtual Timer Value ÁÁÁ RN ÁÁÁÁ EN ÁÁÁ INT ÁÁÁ 0 ÁÁÁÁÁÁÁ Virtual Timer value ÁÁÁ 0 ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ 001 ÁÁÁ ÁÁÁ 0 ÁÁÁÁ ÁÁÁÁ 1 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 0000 ÁÁÁ ÁÁÁ 0 ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ D31 D23 ÁÁÁÁÁ ÁÁÁÁÁ D22 D20 ÁÁÁ ÁÁÁ D19ÁÁÁÁ ÁÁÁÁ D18 ÁÁÁ ÁÁÁ D17 ÁÁÁ ÁÁÁ D16 ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ D15 D1 ÁÁÁ ÁÁÁ D0 WORD 0014h 0000h VIRT2 MAX VALUE 0004H CMD DEF 6 STANDARD COMPARE COMMAND ON VIRTUAL TIMER...

Page 415: ...2 OP1 VIRTUAL TIMER 2 800nS NOTES This example shows the maximum speed resolution in normal mode By changing the timer max value you can modify the PWM period By changing the compare values you can modify the duty cycle It is possible to increase the speed resolution by using the step mode ...

Page 416: ...ATCHDOG MODE A MOV STARTAD 0100H 080H CDSTART START AD CMD DEF INT DIS MOV ENDAD 0100H CDEND END AD MOV 013H PACTSCR SYSCLK DIVIDED BY 4 RESOL 800nS AT 20MHz MAIN PGM MAIN OR 020H PACTSCR ENABLE PACT CMD DEF AREA JMP LOOP MAIN PGM INIT PACT CMD DEF AREA sect CMDEF ENDAD CMD DEF SECTION PROGRAM WORD 0804h 0002h RST OP2 ON 0002H VIRT2 WORD 0824h 0000h SET OP2 ON 0000H VIRT2 WORD 0014h 0000h VIRT2 MA...

Page 417: ... ÁÁÁ RA ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ ST ÁÁÁ ÁÁÁ CA ÁÁÁ ÁÁÁ Pin Select ÁÁÁ ÁÁÁ IC ÁÁÁ ÁÁÁ NX ÁÁÁÁÁ ÁÁÁÁÁ Timer Compare Value ÁÁ ÁÁ 0 ÁÁ ÁÁ 0 ÁÁ ÁÁ 0 ÁÁ ÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁ ÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁ ÁÁ 0 Á Á 0 ÁÁ ÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 1 ÁÁÁÁÁ ÁÁÁÁÁ 0000h ÁÁÁÁÁ ÁÁÁÁÁ D31 D28 ÁÁÁ ÁÁÁ D27 ÁÁ ÁÁ D26 ÁÁÁ ÁÁÁ D25 ÁÁÁ ÁÁÁ D24 ÁÁÁ ÁÁÁ D23 ÁÁÁ ÁÁÁ D22 ÁÁÁ ÁÁÁ D21 ÁÁÁ ÁÁÁ D20 D18...

Page 418: ... ÁÁÁ Pin Select ÁÁÁ ÁÁÁ ÁÁÁ IC ÁÁÁ ÁÁÁ ÁÁÁ NX ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Timer Compare Value ÁÁ ÁÁ 0 ÁÁ ÁÁ 0 ÁÁ ÁÁ 0 ÁÁ ÁÁ 0 ÁÁÁ ÁÁÁ 1 ÁÁ ÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁ ÁÁ 0 Á Á 0 ÁÁ ÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁÁÁ ÁÁÁÁÁ 0004h ÁÁÁÁÁ ÁÁÁÁÁ D31 D28 ÁÁÁ ÁÁÁ D27 ÁÁ ÁÁ D26 ÁÁÁ ÁÁÁ D25 ÁÁÁ ÁÁÁ D24ÁÁÁ ÁÁÁ D23 ÁÁÁ ÁÁÁ D22 ÁÁÁ ÁÁÁ D21 ÁÁÁ ÁÁÁ D20 D18 ÁÁÁ ÁÁÁ D17 ÁÁÁ ÁÁÁ D16 ÁÁÁÁÁ ÁÁÁÁÁ D15...

Page 419: ...Value ÁÁ ÁÁ 0 ÁÁ ÁÁ 0 ÁÁ ÁÁ 0 ÁÁ ÁÁ 0 ÁÁÁ ÁÁÁ 1 ÁÁ ÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁ ÁÁ 0 Á Á 0 ÁÁ ÁÁ 1 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁÁÁ ÁÁÁÁÁ 0009h ÁÁÁÁÁ ÁÁÁÁÁ D31 D28 ÁÁÁ ÁÁÁ D27 ÁÁ ÁÁ D26 ÁÁÁ ÁÁÁ D25 ÁÁÁ ÁÁÁ D24 ÁÁÁ ÁÁÁ D23 ÁÁÁ ÁÁÁ D22 ÁÁÁ ÁÁÁ D21 ÁÁÁ ÁÁÁ D20 D18 ÁÁÁ ÁÁÁ D17 ÁÁÁ ÁÁÁ D16 ÁÁÁÁÁ ÁÁÁÁÁ D15 D0 WORD 00804H 0009H RESET OP2 SECOND OP2 FALLING EDGE ON COMPARE VALUE 0009...

Page 420: ...401 Figure 6 PACT Timing Diagram PACTRESOLUTION CMD DEF SCAN DEFAULTTIMER VIRTUALTIMER OP1 OP2 1ms ...

Page 421: ...E DEBUT OR 003H PACTPRI DISABLE WATCHDOG MODE A MOV STARTAD 0100H 080H CDSTART START AD CMD DEF INT DIS MOV ENDAD 0100H CDEND END AD MOV 014H PACTSCR SYSCLK DIVIDED BY 5 RESOL 1uS AT 20MHZ MAIN PGM MAIN OR 020H PACTSCI ENABLE PACT CMD DEF AREA JMP LOOP MAIN PGM INIT PACT CMD DEF AREA sect CMDEF ENDAD CMD DEF SECTION PROGRAM WORD 00800H 000AH RESET OP1 SECOND OP1 FALLING EDGE ON COMPARE VALUE 000AH...

Page 422: ...tpinevent anoffsettimerstartsincrementingandcontinuesuntilthenextevent Theprogrammer can combine standard compare conditional compare and event compare commands to satisfy his application requirements PWM Generation On Each Event Figure 7 External Event Event Delay and Sync Pulses T1 EXT EVENT EVENT DELAY SYNC PULSES T1 1mS To illustrate this example we use OP2 as external event So it is necessary...

Page 423: ...Á D17 ÁÁÁ ÁÁÁ D16 ÁÁÁÁÁ ÁÁÁÁÁ D15 D0 WORD 00001H 0000h NEXT IS A TIMER DEFINITION CMD DEF 2 VIRTUAL TIMER DEFINITION 2 TS MAX VALUE 0008H ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Maximum Virtual Timer Value ÁÁÁ ÁÁÁ RNÁÁÁÁ ÁÁÁÁ EN ÁÁÁ ÁÁÁ INT ÁÁÁ ÁÁÁ 0 ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ Virtual Timer value ÁÁÁ ÁÁÁ 0 ÁÁÁÁÁÁÁÁÁÁÁ 004 ÁÁÁ 0 ÁÁÁÁ 1 ÁÁÁ 0 ÁÁÁ 0 ÁÁÁÁÁÁÁ 0000 ÁÁÁ 0 ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ D31 D23 ÁÁÁÁÁ ÁÁÁÁÁ D22 D20 ÁÁÁ ÁÁÁ D19 ÁÁÁ...

Page 424: ...Á ÁÁÁ ÁÁÁ EN ÁÁÁ ÁÁÁ ÁÁÁ IM ÁÁ ÁÁ ÁÁ ST ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ Virtual Timer Offset Value ÁÁÁ ÁÁÁ ÁÁÁ 1 ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 00h ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 1 ÁÁÁ ÁÁÁ 0 ÁÁ ÁÁ 0 ÁÁÁÁÁÁ ÁÁÁÁÁÁ 0000h ÁÁÁ ÁÁÁ 1 ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ D31 D24 ÁÁÁ ÁÁÁ D23 ÁÁÁ ÁÁÁ D22 ÁÁÁ ÁÁÁ D21 ÁÁÁ ÁÁÁ D20ÁÁÁ ÁÁÁ D19 ÁÁÁ ÁÁÁ D18 ÁÁÁ ÁÁÁ D17 ÁÁ ÁÁ D16 ÁÁÁÁÁÁ ÁÁÁÁÁÁ D15 D1 ÁÁÁ ÁÁÁ D0 WORD 00004H 0001H MAX ...

Page 425: ...T OP1 ON COMPARE VALUE 0002H ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Reserved ÁÁÁ ÁÁÁ ÁÁÁ EN ÁÁ ÁÁ ÁÁ IR ÁÁÁ ÁÁÁ ÁÁÁ RA ÁÁÁ ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ ÁÁÁ ST ÁÁÁ ÁÁÁ ÁÁÁ CA ÁÁÁ ÁÁÁ ÁÁÁ Pin Select ÁÁÁ ÁÁÁ ÁÁÁ IC ÁÁÁ ÁÁÁ ÁÁÁ NX ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Timer Compare Value ÁÁ ÁÁ 0ÁÁ ÁÁ 0ÁÁ ÁÁ 0 ÁÁ ÁÁ 0 ÁÁÁ ÁÁÁ 1 ÁÁ ÁÁ 0ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁ ÁÁ 0 Á Á 0 ÁÁ ÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁÁÁ ÁÁÁÁÁ 00...

Page 426: ...SABLE WD MODE A MOV STARTAD 0100H 080H CDSTART START AD CMD DEF INT DIS MOV ENDAD 0100H CDEND END AD MOV 014H PACTSCR SYSCLK DIVIDED BY 5 RESOL 1uS AT 20MHZ MAIN PGM MAIN OR 020H PACTSCR ENABLE PACT CMD DEF AREA MOV 020H CPCTL3 EVENT CP6 ON RISING EDGE NO INTERRUPT JMP LOOP MAIN PGM INIT PACT CMD DEF AREA sect CMDEF ENDAD CMD DEF SECTION PROGRAM WORD 00800H 0002H RESET OP1 ON COMPARE VALUE 0002h W...

Page 427: ...1D4h MAX EVENT COUNTER VALUE 05h PACT Command Definition Initialization CMD DEF 1 DUMMY STANDARD COMPARE COMMAND ON DEFAULT TIMER 1 TS USE ONLY TO IDENTIFY NEXT ENTRY AS A TIMER DEFINITION NO ACTION ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Reserved ÁÁÁ ÁÁÁ ÁÁÁ EN ÁÁ ÁÁ ÁÁ IR ÁÁÁ ÁÁÁ ÁÁÁ RA ÁÁÁ ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ ÁÁÁ ST ÁÁÁ ÁÁÁ ÁÁÁ CA ÁÁÁ ÁÁÁ ÁÁÁ Pin Select ÁÁÁ ÁÁÁ ÁÁÁ IC ÁÁÁ ÁÁÁ ÁÁÁ NX ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Tim...

Page 428: ...Á IM ÁÁ ÁÁ ST ÁÁÁÁÁÁ ÁÁÁÁÁÁ Virtual Timer Offset Value ÁÁÁ ÁÁÁ 1 ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 05h ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 1 ÁÁÁ ÁÁÁ 0 ÁÁ ÁÁ 0 ÁÁÁÁÁÁ ÁÁÁÁÁÁ 0000h ÁÁÁ ÁÁÁ 1 ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ D31 D24 ÁÁÁ ÁÁÁ D23 ÁÁÁ ÁÁÁ D22 ÁÁÁ ÁÁÁ D21 ÁÁÁ ÁÁÁ D20 ÁÁÁ ÁÁÁ D19 ÁÁÁ ÁÁÁ D18 ÁÁÁ ÁÁÁ D17 ÁÁ ÁÁ D16 ÁÁÁÁÁÁ ÁÁÁÁÁÁ D15 D1 ÁÁÁ ÁÁÁ D0 WORD 00504H 0001H OFFSET TIMER DEFINITION MAX EVENT COUNT...

Page 429: ...Value ÁÁÁ ÁÁÁ 1 ÁÁÁ ÁÁÁ SA ÁÁÁ ÁÁÁ CA ÁÁÁÁ ÁÁÁÁ Pin Select ÁÁÁ ÁÁÁ ICÁÁÁ ÁÁÁ NXÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ Timer Compare Value ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 03h ÁÁÁ ÁÁÁ 1 ÁÁÁ ÁÁÁ 1 ÁÁÁ ÁÁÁ 0 ÁÁÁÁ ÁÁÁÁ 000 ÁÁÁ ÁÁÁ 0ÁÁÁ ÁÁÁ 0 ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ 0001h ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ D31 D24 ÁÁÁ ÁÁÁ D23ÁÁÁ ÁÁÁ D22 ÁÁÁ ÁÁÁ D21 ÁÁÁÁ ÁÁÁÁ D20 D18 ÁÁÁ ÁÁÁ D17 ÁÁÁ ÁÁÁ D16 ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ D15 D0 WORD 003C0H 0001H RESET OP1 ON EVT CMP 03h T...

Page 430: ...4ms 1ms 2ms Action On Event N 3 N 4 N 5 PACT RESOLUTION CMD DEF SCAN OFFSET TIME R OP1 INTERNAL EVT SYNC EXT EVENT ON CP6 EVENT COUNTER T4 3ms ACTION DELAY 3 RESOL 3ms ACTION DELAY 3 RESOL 3ms 1ms NOTE In this example the jitter is 1 resolution because of the external event synchronization OP2 connected to CP6 All timing delays T1 to T5 have a1 ms jitter ...

Page 431: ...QU 01ccH INIT PACT PERIPHERAL FRAME OR 003H PACTPRI DISABLE WD MODE A OR 006H CPPRE RESET EVENT COUNTER CP6 EVENT ONLY NO CAPTURE MOV STARTAD 0100H 080H CDSTART START AD CMD DEF INT DIS MOV ENDAD 0100H CDEND END AD MOV 014H PACTSCR SYSCLK DIVIDED BY 5 RESOL 1mS AT 20MHZ AND 0FDH CPPRE DISABLE RESET EVENT COUNTER MAIN PGM MAIN OR 020H PACTSCR ENABLE PACT CMD DEF AREA MOV 020H CPCTL3 EVENT CP6 ON RI...

Page 432: ...its Each PACT input pin CP1 to CP6 has its own interrupt source which can inform the CPU that a capture has occurred The purpose of these examples is to show how the PACT capture functions can be used Using Dedicated 32 Bit Capture Registers This example shows how it can measure a delay between two events one on CP1 the other on CP2 Figure 11 CP1 and CP2 Events T CP1 CP2 T CP2 CAPTURE CP1 CAPTURE ...

Page 433: ...ÁÁ D18 ÁÁÁ ÁÁÁ D17 ÁÁÁ ÁÁÁ D16 ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ D15 D1 ÁÁÁ ÁÁÁ D0 WORD 00804H 0000H MAX VALUE 1000h D19 0 CMD DEF 3 STANDARD COMPARE COMMAND ON VIRTUAL TIMER 1 TS RESET OP1 ON COMPARE VALUE 0010H SET ON ZERO ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Reserved ÁÁÁ ÁÁÁ ÁÁÁ EN ÁÁ ÁÁ ÁÁ IR ÁÁÁ ÁÁÁ ÁÁÁ RA ÁÁÁ ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ ÁÁÁ ST ÁÁÁ ÁÁÁ ÁÁÁ CA ÁÁÁ ÁÁÁ ÁÁÁ Pin Select ÁÁÁ ÁÁÁ ÁÁÁ IC ÁÁÁ ÁÁÁ ÁÁÁ NX ÁÁÁÁÁ ÁÁÁÁÁ Á...

Page 434: ...PACTSCR ENABLE PACT CMD DEF AREA EINT ENABLE INTERRUPT MN MOV 092H CPCTL1 CAPTURE ON CP1 RISE AND CP2 FALL INT CP2 ENABLE BLE JMP MN LOOP MAIN PGM INTERRUPT CAPTURE CP2 ITCP2 MOV 000H CPCTL1 DISABLE CP1 CP2 CAPTURE AND CLEAR ITCP2 FLAG STORE CP1 CAPTURE IN REGISTERS R0F9 R0FA R0FB MOV 01F9H A MOV A R0F9 MOV 01FAH A MOV A R0FA MOV 01FBH A MOV A R0FB STORE CP2 CAPTURE IN REGISTERS R0F5 R0F6 R0F7 MOV...

Page 435: ...0h VIRT1 MAX VALUE 8000H WORD 0001h 0000h NEXT IS A DEF NOTES In this example the jitter is 1 resolution because of the external event synchronization OP1 connected to CP1 and CP2 All timing delays T1 to T5 have 1 ms jitter The jitter average is 1 2 resolution in case of asynchronous external events The measurement value is stored in registers R0E5 R0E6 R0E7 LSB It is always equal to the CMD DEF 3...

Page 436: ...resolution will not be captured For our example the PACT resolution is SYSCLK 5 1ms AT 20 MHz We generate a PWM on OP1 connected to CP6 in order to perform CP6 events 3 CMD DEF 1 dummy next def 1 virtual timer DEFINITION 1 standard compare action on OP1 BUFFER USED TO CAPTURE CP6 EVENTS SIZE 4 x 32 BITS REGISTERS IN MODE A INT BUFF CP6 CAPTURE ON RISING EDGE PACT Command Definition Initialization ...

Page 437: ... D19 0 CMD DEF 3 STANDARD COMPARE COMMAND ON VIRTUAL TIMER 1 TS ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Reserved ÁÁÁ ÁÁÁ ÁÁÁ EN ÁÁ ÁÁ ÁÁ IR ÁÁÁ ÁÁÁ ÁÁÁ RA ÁÁÁ ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ ÁÁÁ ST ÁÁÁ ÁÁÁ ÁÁÁ CA ÁÁÁ ÁÁÁ ÁÁÁ Pin Select ÁÁÁ ÁÁÁ ÁÁÁ IC ÁÁÁ ÁÁÁ ÁÁÁ NX ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Timer Compare Value ÁÁ ÁÁ 0ÁÁ ÁÁ 0ÁÁ ÁÁ 0 ÁÁ ÁÁ 0 ÁÁÁ ÁÁÁ 1 ÁÁ ÁÁ 0ÁÁÁ ÁÁÁ 1 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁ ÁÁ 0 Á Á 0 ÁÁ ÁÁ 1...

Page 438: ...PPRE EQU P04D CP input control register PACTSCR EQU p040 Setup control register ENDAD EQU 01d8H INIT PACT PERIPHERAL FRAME OR 003H PACTPRI DISABLE WATCHDOG MODE A MOV 010H B LDSP MOV 002H CPPRE RST EVENT COUNTER NO CAPTURE PRESCALER MOV STARTAD 0100H 080H CDSTART START AD CMD DEF INT DIS MOV ENDAD 0100H CDEND END AD MOV 013H PACTSCR SYSCLK DIVIDED BY 4 RESOL 800nS AT 20MHz MOV 0F2H P043 INIT BUFFE...

Page 439: ... R0EF SBB R0F2 R0EE SBB R0F1 R0ED RESULT STORED IN REGISTER R0ED R0EE R0EF RETURN TO MAIN PGM RTI BFULL MOV 0EBH B B STORAGE POINTER CALL STORE CP6 PERIOD MEASUREMENT SUB R0EB R0E7 SBB R0EA R0E6 SBB R0E9 R0E5 RESULT STORED IN REGISTER R0E5 R0E6 R0E7 RETURN TO MAIN PGM RTI SUBROUTINE STORE STORE STORE BUFFER CAPTURE 1 IN REGISTERS R0F0 R0F1 R0F2 R0F3 MOV B R090 R090 END STORAGE POINTER SUB 009H R09...

Page 440: ...E 0008H WORD 0001h 0000h NEXT IS A DEF NOTES In this example the jitter equals one resolution because of the external event synchronization OP1 connected to CP6 All timing delays T have a 1 ms jitter The jitter average is half resolution in case of asynchronous external events The measurement value is stored in registers R0E5 R0E6 R0E7 LSB or R0ED R0EE R0EF LSB BychangingCMD DEF2virtualtimermaximu...

Page 441: ...ime slots available are used to generate OP1 and OP2 PWM It is possible to improve significantly the PWM speed by changing the resolution and using the STEP mode in this example Figure 13 Step Mode PWM OP1 OP2 resol 600nS T 1 2 ms PACT Configuration PACT RESOLUTION 600nS SYSCLK 3 5 x 2 TS AVAILABLE in STEP MODE 10 TS CMD DEF CONFIG 1 STEP 1 NEXTDEF 2 VIRT TIMER 4 STANDARD COMPARE 10 TS BUFFER NOT ...

Page 442: ...DEF 3 VIRTUAL TIMER 1 DEFINITION 2 TS MAX VALUE 0000H ÁÁÁÁÁÁÁÁÁÁÁ Maximum Virtual Timer Value ÁÁÁ RN ÁÁÁÁ EN ÁÁÁ INT ÁÁÁ 0 ÁÁÁÁÁÁÁ Virtual Timer value ÁÁÁ 0 ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ 000 ÁÁÁ ÁÁÁ 0 ÁÁÁÁ ÁÁÁÁ 1 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 0000 ÁÁÁ ÁÁÁ 0 ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ D31 D23 ÁÁÁÁÁ ÁÁÁÁÁ D22 D20 ÁÁÁ ÁÁÁ D19ÁÁÁÁ ÁÁÁÁ D18 ÁÁÁ ÁÁÁ D17 ÁÁÁ ÁÁÁ D16 ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ D15 D1 ÁÁÁ ÁÁÁ D0 WORD 0004h 0000...

Page 443: ...Á ÁÁÁ D23 ÁÁÁ ÁÁÁ D22 ÁÁÁ ÁÁÁ D21 ÁÁÁ ÁÁÁ D20 D18 ÁÁÁ ÁÁÁ D17 ÁÁÁ ÁÁÁ D16 ÁÁÁÁÁ ÁÁÁÁÁ D15 D0 WORD 0824h 0001h SET OP2 ON 0001H VIRT1 CMD DEF 8 STANDARD COMPARE COMMAND ON VIRTUAL TIMER 1 1 TS RESET OP2 ON VIRTUAL TIMER 1 VALUE 0000H ÁÁÁÁÁ ÁÁÁÁÁ Reserved ÁÁÁ ÁÁÁ EN ÁÁ ÁÁ IR ÁÁÁ ÁÁÁ RA ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ ST ÁÁÁ ÁÁÁ CA ÁÁÁ ÁÁÁ Pin Select ÁÁÁ ÁÁÁ IC ÁÁÁ ÁÁÁ NX ÁÁÁÁÁ ÁÁÁÁÁ Timer Compare Value ...

Page 444: ...MODE A MOV STARTAD 0100H 080H CDSTART START AD CMD DEF INT DIS MOV ENDAD 0100H 04H CDEND END AD MOV 012H PACTSCR SYSCLK DIVIDED BY 3 RESOL 600ns AT 20MHz MAIN PGM MAIN OR 020H PACTSCR ENABLE PACT CMD DEF AREA JMP LOOP MAIN PGM INIT PACT CMD DEF AREA sect CMDEF ENDAD CMD DEF SECTION PROGRAM WORD 0804h 0000h RST OP2 ON 0000H VIRT2 WORD 0824h 0000h SET OP2 ON 0000H VIRT1 WORD 0A00h 0001h SET OP1 ON 0...

Page 445: ... 0 ÁÁÁ ÁÁÁ 0 ÁÁ ÁÁ 0ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁ ÁÁ 0 Á Á 0 ÁÁ ÁÁ 0 ÁÁÁ ÁÁÁ 0 ÁÁÁ ÁÁÁ 1 ÁÁÁÁÁ ÁÁÁÁÁ 0000h ÁÁÁÁÁ D31 D28 ÁÁÁ D27 ÁÁ D26 ÁÁÁ D25 ÁÁÁ D24 ÁÁÁ D23 ÁÁÁ D22 ÁÁÁ D21 ÁÁÁ D20 D18 ÁÁÁ D17 ÁÁÁ D16 ÁÁÁÁÁ D15 D0 WORD 00001H 00000H NEXT IS A TIMER DEFINITION CMD DEF 3 SCI BAUD RATE TIMER DEFINITION 2 TS MAX VALUE 0018H D19 0 ÁÁÁÁÁÁÁÁÁÁÁ Maximum Virtual Timer Value ÁÁÁ RN...

Page 446: ...ntrol register ENDAD EQU 01E4H SCICTLP EQU P045 PACT SCI control register RXBUFP EQU P046 PACT SCI RX data register TXBUFP EQU P047 PACT SCI TX data register INIT PACT PERIPHERAL FRAME DEBUT OR 003H PACTPRI DISABLE WATCHDOG MODE A MOV 010H B INIT STACK POINTER LDSP MOV STARTAD 0100H 080H CDSTART START AD CMD DEF INT DIS MOV ENDAD 0100H CDEND END AD MOV 014H PACTSCR SYSCLK DIVIDED BY 5 RESOL 1us AT...

Page 447: ...ON OK JNZ ERROR RTI ERROR DINT DISABLE INT TO STOP TRANSMISSION IN CASE OF ERROR JMP SCI INTERRUPT VECTOR sect VECTSC8I 07F9CH SCI INTERRUPT VECTORS WORD ITTXD SCI TRANSMIT VECTOR WORD ITRXD SCI RECEIVE VECTOR INIT PACT CMD DEF AREA sect CMDEF ENDAD CMD DEF SECTION PROGRAM WORD 0A20h 000Ch SET OP1 ON 000CH VIRT INV ACTION ON ZERO VIRT WORD 00C7h 0000h VIRT1 MAX VALUE 000cH WORD 0001h 0000h NEXT IS...

Page 448: ...utput Pins Actions Figure 16 PACT Dual Port Ram Mapping Mode A Mode B 0180h Cmd End 01F4h 01F8h 01FCh General Purpose RAM Command Definition Area Circular Buffer Event Cnt Event Cnt Event Image Capture by CP2 Capture by CP1 20 Bit Timer Image 01F3h 01F7h 01F8h 01FFh Cmd Start 0180h Cmd End General Purpose RAM Command Definition Area Circular Buffer Cmd Start Event Cnt Event Cnt Event Image Capture...

Page 449: ...cular Buffer in Dual Port RAM Dedicated Capture Register 1 Dedicated Capture Register 2 Dedicated Capture Register 3 Dedicated Capture Register 4 Circular Buffer 32 Bit Captures 8 Bit Event Counter 20 Bit Timer Counter CP1 CP2 CP3 CP4 CP5 CP6 Mode Event Only 3 Bit Prescale PACT Prescaled Clock ...

Page 450: ...top and start the timer D19 Range bit RN used in conjunction with D20 22 to define the maximum value D20 22 Define a further three bits of the maximum count for the virtual timer Either D13 14 or 15 of the virtual timer if the range bit 1 or D1 2 or 3 if the precision bit 0 The undefined bits of the maximum count for the virtual timer are set to 1 if the range bit 1 or set to 0 if the range bit 0 ...

Page 451: ...ree bits of the maximum count of the virtual timer Either D13 14 or 15 of the virtual timer if the range bit 1 or D1 2 or 3 if the range bit 0 Theundefinedbitsofthemaximumcountforthevirtualtimeraresetto1ifrange bit 1 or to set to 0 if the range bit 0 D23 31 Sets the radical of the maximum count of the virtual timer Used with D20 22 to specify the maximum count of the virtual timer When the virtual...

Page 452: ...op and start the timer D19 Inhibit clear HC Active 1 When this bit is set the virtual offset timer defined will not be reset to zero when an event CP6 occurs If this bit is cleared the virtual offset timer will be automatically reset to zero on every event on CP6 D20 Reset default timer RD Active 1 Clear default timer when event counter reaches the maximum value D24 31 D21 Virtual capture VC Activ...

Page 453: ...on compare IC Active 1 Interrupt when the compare value D0 D15 is matched by the reference timer D18 20 Pin selection Selects the output pin that will be modified when the compare value is matched The pin number is the binary value of the bits D31 D20 D19 or D18 plus 1 D21 Compare action CA Sets or resets the pin defined by pin selection pin offset when the compare value is matched by the referenc...

Page 454: ... D24 31 plus 1 D18 20 Pin selection Selects an output pin whose state is modified when the compare value is matched The pin number is the binary value of D20 18 plus 1 except the binary value 111 which disables any pin action Therefore OP8 is not available for this command D21 Compare action CA Sets or resets the pin defined by pin selection when both compare values are matched by the reference ti...

Page 455: ...lection Selects the output pin where state will be modified when the compare value is matched The pin number is the binary value of the bits D20 to 18 1 20 LSB 18 MSB D21 Compare action 1 A1 Sets or resets the output pin defined by pin selection pin offset when the event 1 compare value D0 D7 is matched by the event counter These actions occur with a delay of three resolutions set 1 clear 0 D22 St...

Page 456: ...ÁÁ PACT OP8 STATE ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ PACT OP7 STATE ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ PACT OP6 STATE ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ PACT OP5 STATE ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ PACT OP4 STATE ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ PACT OP3 STATE ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ PACT OP2 STATE ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ PACT OP1 STATE Á Á Á ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ CDFLAGS P049 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ CMD DEF INT 7 FLAG ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ CMD DEF INT 6 FLAG ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ CMD DEF INT 5 FLAG ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ CMD DEF INT 4 FLAG...

Page 457: ...ÁÁÁÁÁÁ PACT SCI TX INT ÁÁÁÁÁÁ ÁÁÁÁÁÁ PACT TX RDY ÁÁÁÁÁ ÁÁÁÁÁ PTXINT ÁÁÁÁ ÁÁÁÁ 2 ÁÁÁÁ ÁÁÁÁ Group 2 ÁÁÁÁÁ ÁÁÁÁÁ 7F9Eh 7F9Fh ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ PACT SCI RX INT ÁÁÁÁÁÁ ÁÁÁÁÁÁ PACT RXRDY ÁÁÁÁÁ ÁÁÁÁÁ PRXINT ÁÁÁÁ ÁÁÁÁ 1 ÁÁÁÁ ÁÁÁÁ PACT Group 3 ÁÁÁÁÁ ÁÁÁÁÁ 7FA0h 7FA1h ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ PACT CMD DEF Entry 0 ÁÁÁÁÁÁ ÁÁÁÁÁÁ CMD DEF INT 0 FLAG ÁÁÁÁÁ ÁÁÁÁÁ CDINT 0 ÁÁÁÁ ÁÁÁÁ 1 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ 7FA2h 7F...

Page 458: ... III Module Specific Application Design Aids Part III contains six sections RESET Operations 99 SPI and SCI Modules 105 Timer and Watchdog Modules 199 Analog to Digital Modules 309 PACT Module 375 I O Pins 439 ...

Page 459: ...440 ...

Page 460: ...441 Proper Termination of Unused I O Pins Michael S Stewart Microcontroller Products Semiconductor Group Texas Instruments ...

Page 461: ...442 ...

Page 462: ...thispincircuitry will then be self biased to either a logical high or low state In this condition current paths will be generated allowing unwanted power consumption This condition is normally called the floating nodes problem and the symptom that is most commonly seen when the device does not have any unused input pins connected to VCC or VSS is that the low power current will initially fall to t...

Page 463: ... best recommendation for unused I O pins Alternative solutions are presented in later sections however potential problems outlined for each alternative solution outweigh the potential cost savings of using one resistor Another system application that will generate the need to terminate an unused pin will be when an external clock signal is driven in on the XTAL2 CLKIN pin The associated XTAL1 pin ...

Page 464: ...This option is not available for input only pins The main advantage of this solution is the zero added system cost This solution is ideal for applications that do not use low power mode It can be a problem however when microcontrollers are subjected to harsh environments that contain violent electrical noise spikes VCC and VSS swings can cause the program counter of the microcontroller to be corru...

Page 465: ...s acceptable Disadvantages of this solution are similar to those described on the previous page External electrical conditions could corrupt the program counter to cause I O pins to change their initialization For example if two I O pins were tied together and pulled low via a common resistor see Figure 4 inappropriate software execution could alter these pins If one pin was altered to be an outpu...

Page 466: ...ed in If the pin is initialized as an input only leakage current can occur If the pin is initialized as an output low then the current depends on the voltage drop from the VOL level and VSS across the external resistor If the pin is initialized as an output high the current depends on the voltage drop from the VOH level and VSS across the external resistor The larger the resistor value used the le...

Page 467: ...448 ...

Page 468: ...449 Part IV EEPROM Programming Part IV contains two sections EEPROM Self Programming 449 Bootstrap Programs 457 ...

Page 469: ...450 ...

Page 470: ...451 EEPROM Self Programming With the TMS370 Microcontroller Products Semiconductor Group Texas Instruments ...

Page 471: ...452 ...

Page 472: ... can occur when an interrupt routine accesses any EEPROM location interrupting the EEPROG routine between writing to the EEPROM location and setting the EXE bit DEECTL 0 You can program unprotected data EEPROM using only the VCC power supply Enter the write protection override WPO mode by placing 12 V on the MC pin when programming protected data EEPROM The following program is used to write to an...

Page 473: ...all possible bit combinations In this example the memory address contains x1100 and x1010 is programmed to that address Before calling the EEPROG routine the program writes new data to the EEPROM address located in register ADDR1 1 ADDR1 and then passes data to register A that specifies either a write ones or a write zeros operation The program provides actual values at each step PROGRAM Routine A...

Page 474: ...3 program 1s MOV TEMP2 A x1010 CALL EEPROG x1010 Program 0s Verify the programming operation LASTCHK MOV ADDR1 A x1010 Check new memory against wanted memory CMP TEMP2 A If equal then exit JEQ EXITW Error handling routine here EXITW RTS ...

Page 475: ...456 ...

Page 476: ...457 Part IV EEPROM Programming Part IV contains two sections EEPROM Self Programming 449 Bootstrap Programs 457 ...

Page 477: ...458 ...

Page 478: ...459 Bootstrap Program for the TMS370 Microcontroller Products Semiconductor Group Texas Instruments ...

Page 479: ...460 ...

Page 480: ...R04 Data length TEMP EQU R07 Temporary register TEMP1 EQU R14 Temporary register 1 TEMP2 EQU R12 Temporary register 2 program TEXT 7300H MOV 0A0H B Initialize stack LDSP LAST MOV 0FFH SPICCR Initialize SPI MOV 047H SPICCR Program SPI for 8 bit data MOV 03 SPICTL Program SPI for slave and enable inter MOV 02 SPIPC1 Enable SPICLk pin MOV 020H SPIPC2 Enable SPISIMO and SPISOMI pin START1X CLR B Reset...

Page 481: ...1 CLR B Clear index JMP AGAIN Get more data PROGRAM TO WRITE 0s AND 1s TO DATA OR PROGRAM EEPROM PROG MOV A EECTL B Load DEECTL EINT MOVW 2778 TEMP1 Wait for 10 ms for EEPROM write WAIT10 INCW 1 TEMP1 JC WAIT10 CLR A Reset execution bit in DEECTL MOV A EECTL B EXITPROG RTS ROUTINE TO COMPARE THE CONTENT OF PROGRAMMED BYTE WITH DESIRED VALUE LASTCHK MOV DATAL 2 A Load the EEPROM content CMP TEMP2 A...

Page 482: ...463 Bootstrap Program for the SPI in Slave Mode Microcontroller Products Semiconductor Group Texas Instruments ...

Page 483: ...464 ...

Page 484: ...er SPIBUF EQU P037 SPI receive data buffer register SPIDAT EQU P039 SPI serial data register SPIPC1 EQU P03D SPI port control register 1 SPIPC2 EQU P03E SPI port control register 2 SPIPRI EQU P03F SPI priority DEECTL EQU P01A Data EEPROM control register Program the SPI in Slave Mode TEXT 7F9CH INIT MOV 0F7H SPICCR Initialize SPI MOV 047H SPICCR Program SPI for 8 bit data MOV 03 SPICTL Program SPI...

Page 485: ...466 ...

Page 486: ...467 Bootstrap Program for the TMS370 in Master Microcontroller Products Semiconductor Group Texas Instruments ...

Page 487: ...468 ...

Page 488: ...he maximum No of bytes that can be transmitted COMMAND EQUR16 R16 has the command word MASK EQU80H Mask for EEPROM programming condition Program to transmit program Remember that the last byte of program has to be sent first The last byte sent must be first byte of program In the beginning dummy bits may have to be sent depending on the program length TEXT 7000H MOV 0A0H B Initialize the stack LDS...

Page 489: ... in packets of 3F NEXT CALL PROG2 Program to send bytes 3F RTS Return to calling program Program to reset flag in slave RESET CLR A A 0 for eeprogramming completion MOV A SPIDAT Transmit it LOOP10 BTJZ 40H SPICTL LOOP10 Wait until transmitted MOV SPIBUF A Read to clear interrupt flag JMP EXIT Return to main program Subroutine PROG1 creates a command word and transmit the bytes in the packets of 3F...

Page 490: ...PICTL LOOP4 Wait till transmitted MOV SPIBUF A Read to clear interrupt flag MOV STRT 1 A Load high byte of destination address MOV A SPIDAT Transmit it LOOP5 BTJZ 40H SPICTL LOOP5 Wait intil transmitted MOV SPIBUF A Read to clear interrupt flag MOV STRT A Load low byte of destination address MOV A SPIDAT Transmit it LOOP6 BTJZ 40H SPICTL LOOP6 Wait until transmitted MOV SPIBUF A Read to clear inte...

Page 491: ...472 ...

Page 492: ...473 Part V External Memory Expansion Examples ...

Page 493: ...474 ...

Page 494: ...475 Using Memory Expansion in Microcomputer Mode With Internal Memory Disabled Microcontroller Products Semiconductor Group Texas Instruments ...

Page 495: ...476 ...

Page 496: ...bus as expected To prevent corrupting the bus expansion mode The addresses of XPORT2 and DPORT1 should not be used as external Addresses used to control general purpose I Os should not be used as external addresses Use of read modify instructions at 102Xh locations is not available since it would read external data and write or modify the internal I O configuration registers located at the same ad...

Page 497: ...478 ...

Page 498: ...479 Interfacing and Accessing External Memory Microcontroller Products Semiconductor Group Texas Instruments ...

Page 499: ...480 ...

Page 500: ... with the following Three TMS27C256s each providing 32K bytes of EPROM ROM1 ROM2 and ROM3 at U2 to U4 for a total of 96K bytes Two HM626LP 15s each providing 8K bytes of RAM RAM1 and RAM2 at U6 and U7 for a total of 16K bytes A peripheral device U5 needing up to 64 bytes of memory address space that interfaces to the memory select process This uses a total memory of 116K bytes 112K bytes of extern...

Page 501: ...x 8 Static RAM R W CSE2 CSE1 CSPF CSH3 CSH2 CSH1 ROM1 ROM2 ROM3 RAM1 RAM2 The devices used in the TMS370 interface example circuit are TMS370C050 8 bit CMOS microcontroller TMS27C256 32K x 8 EPROM HM626LP Hitachi 8K x 8 RAM Table 1 Timing Specifications for the TMS27C256 25 EEPROM Devices Symbol Description Min Max ta A Access time from address 250 ns ta E Access time from enable 250 ns tdis Outpu...

Page 502: ...ry accesses in three different ways Use the AUTOWAIT DISABLE bit at SCCR1 4 to add one wait state to all external accesses Use the PF AUTOWAIT bit at SCCR0 5 to add two wait states to the external peripheral file access Allow the external device to pull the WAIT pin low and add as many wait states as required Table 3 shows the various combinations Table 3 Wait State Control Bits Wait State Control...

Page 503: ...s td AV DV R Delay time address valid to read data valid 1 5 tc 115 ns td AV WTV Delay time address valid to WAIT valid tc 115 ns td AV EH Delay time address valid to EDS high end of write 1 5 tc 85 ns tc system clock cycle time 4 CLKIN If wait states PFWait or the autowait feature is used add tc to this value for each wait state invoked If the autowait feature is enabled the WAIT input may assume...

Page 504: ...w cost applications with cheaper slower memory devices TheHM6264 15RAMcanextendtheTMS370 sminimumaddress to dataset uptimewithnowaitstates When you access external RAM comparable to that of the Hitachi device you can turn off the autowait feature to speed up the system A peripheral device can have up to 585 ns to respond to the TMS370 if the peripheral frame PF wait states are enabled If the extra...

Page 505: ...ive Requirements The TMS370 and the memory device should not drive the memory at the same time This can lead to increasedstressandnoisespikingontheVCCandVSSlinesandreducethereliabilityofthedevice Memory devices often continue to drive the memory for a short time after the chip select signal goes high This normally doesn t present a problem unless the chip select signal is delayed by interface circ...

Page 506: ... provide data up to this point or incorrect data may be read Mostmemories will continue to hold or drive the data memory for a short time after they are deselected although the data may or may not be valid After that period the memories put their data outputs into the high impedance state Figure 5 Read Data Hold After Chip Select High Timing tv A td EH D R EDS CSxx From TMS370 Data Required by TMS...

Page 507: ...s Name Description Formula Time tW TMS370 no wait pulse width provided tc 80 120 ns tW TMS370 PF wait pulse width provided 3 tc 80 520 ns tCW HM6264 15 pulse width required 100 ns Write Data Set Up Time Requirements The write data set up time is the period the RAM needs to receive data before the chip select signal goes high inactive Table 10 Write Data Set Up Timing Specifications Name Descriptio...

Page 508: ... optimize your system performance Lower Cost If system cost is important use slower memories that are less expensive The slowest TMS27C256 25 EPROM has an access time of 250 ns Access time from address to valid data 5 MHz tc 200 TMS370 1 wait requires data tD AV DV R 2 5 tc 115 385 ns TMS27C256 25 provides data tA A 250 ns ok Access time from enable low to valid data 5 MHz tc 200 TMS370 1 wait req...

Page 509: ... or banks one at a time during a read or write cycle Figure 8 and Table 12 define the registers and their addresses used in these examples In the interface example in Figure 1 page 482 the three EPROM devices ROM1 ROM3 each use addresses 8000h though FFFFh Only one EPROM device or bank selected by CSH1 CSH2 or CSH3 can be allowed to read data at a single time The two RAM devices are each mapped at...

Page 510: ...2Bh P02B Port C Direction DPORT1 102Ch P02C Port D Control Register 1 DPORT2 102Dh P02D Port D Control Register 2 DDATA 102Eh P02E Port D Data DDIR 102Fh P02F Port D Direction Equates for Examples The following equates apply to the code examples herein SCCR0 EQU P010 System control config register 0 SCCR1 EQU P011 System Control config register 1 APORT2 EQU P021 Port A control register 2 BPORT2 EQ...

Page 511: ...whether the port is configured as an I O data bus address bus or control signal If DPORT1 1 and xPORT2 0 the function is not valid The variable x represents port letters A B C D G and H xPORT1 exists for DPORT only These pins can be configured only as general purpose I O Pins D1 D2 D5 G0 G7 and H0 are not available in microprocessor mode Ports vary for each device See the applicable device pin des...

Page 512: ... 1 instruction if conditions of other chip selects were known Changing to EPROM Bank 3 and RAM Bank 2 Routine This routine provides switching from one EPROM bank to another while operating from an EPROM bank Only one instruction in EPROM bank 2 is needed The code within the EPROM banks must be synchronized andtheinstructionattheaddressafterthemoveinstructionmustbeavalidinstructionwithin the new EP...

Page 513: ...494 ...

Page 514: ...495 Read Write Serial EEPROM Data on the TMS370 Microcontroller Products Semiconductor Group Texas Instruments ...

Page 515: ...496 ...

Page 516: ...or the read write serial EEPROM data routine 1 The delay timing is based on a 5 MHz SYSCLK 2 This routine works with National or XICOR 64 4 devices 3 Data is arranged as seven 8 bit bytes plus an 8 bit checksum last byte 4 The last byte contains the checksum 5 I O port assignments D0 is the clock output D1 is the select output D2 is the read data input D3 is the write data output ...

Page 517: ...00110b A READ RAM 0 CALL RDXIC MOV 10001110b A READ RAM 1 CALL RDXIC MOV 10010110b A READ RAM 2 CALL RDXIC MOV 10011110b A READ RAM 3 CALL RDXIC MOV 10000010b A ENTER SLEEP MODE CALL XICINS CALL DESEEP DESELECT EEPROM JMP RDEEP2 DO COMMON EEPROM PROCESSING RDEEP1 CALL DESEEP MOV 10000000b A READ RAM 0 CALL RDNAT MOV 10000001b A READ RAM 1 CALL RDNAT MOV 10000010b A READ RAM 2 CALL RDNAT MOV 100000...

Page 518: ... RAM 0 CALL WTXIC MOV 10001011b A WRITE RAM 1 CALL WTXIC MOV 10010011b A WRITE RAM 2 CALL WTXIC MOV 10011011b A WRITE RAM 3 CALL WTXIC MOV 10000001b A STORE RAM DATA INTO E2PROM CALL XICINS CALL DL10MS WAIT 10 MILLISECONDS JMP WTEEP2 WTEEP1 MOV 00110000b A ERASE WRITE ENABLE CALL NATINS CALL DESEEP MOV 00100000b A ERASE E2PROM CALL NATINS CALL DESEEP CALL DL30MS DESELECT FOR 30 MILLISECONDS MOV 01...

Page 519: ... XICOR PART THEN SEND DATA WTXIC CALL XICINS CALL WTDAT JMP DESEEP SEND 16 BITS OF DATA TO EEPROM WTDAT MOV 16 B WTDAT1 CALL SHFTNV JC WTDAT2 CALL CLKZRO JMP WTDAT3 WTDAT2 CALL CLKONE WTDAT3 DJNZ B WTDAT1 JMP DESEEP SEND INSTRUCTION TO EEPROM FROM A NATINS FOR NATIONAL XICINS FOR XICOR NATINS CALL SELEEP CALL CLKONE JMP INS1 XICINS CALL SELEEP INS1 MOV 8 B INS2 RLC A JC INS3 CALL CLKZRO JMP INS4 I...

Page 520: ...M CLKZRO AND 11111110b DPORT CLKEEP OR 00001000b DPORT AND 11110111b DPORT RTS SHIFT EEPROM DATA LEFT 1 BIT LEAVES BIT SHIFTED OUT IN CARRY SHIFTS CARRY VALUE ON CALL INTO LAST BIT OF EEPROM SHFTNV EQU RLC EEPROM 7 RLC EEPROM 6 RLC EEPROM 5 RLC EEPROM 4 RLC EEPROM 3 RLC EEPROM 2 RLC EEPROM 1 RLC EEPROM RTS END ...

Page 521: ...502 ...

Page 522: ...3 Part VI Specific System Application Design Aids Part VI contains two sections EMI Reduction 503 Cost Effective Input Protection Circuitry for the Texas Instruments TMS370 Family of Microcontrollers 525 ...

Page 523: ...504 ...

Page 524: ...505 PCB Design Guidelines for Reduced EMI Robert DeMoor Microcontroller Products Semiconductor Group Texas Instruments ...

Page 525: ...506 ...

Page 526: ...ng to fix EMI problems after a design has reached the testing phase of development Consequently following a few guidelines for printed circuit board PCB design at the beginning of a project can help to minimize the system s EMI while adding little or no cost to the system Background and Theory Knowledge and understanding of a few fundamental concepts can be exercised toward the design of an electr...

Page 527: ... connectors and wiring harnesses In other words any conductive element on or connected to a PCB can act as an antenna The challenge is to reduce the efficiency of these antennas If a radio station has a source broadcasting power of 100 megawatts but has no antenna to broadcast from nobody will hear it In much the same way a well designed PCB can minimize the amount of radiation that is transmitted...

Page 528: ...arge signal return loop would be created This would undesirably provide a more efficient radiating and receiving antenna for high frequency EMI than if path B were there Loops of this nature should be avoided Figure 2 Paths of Least Impedance vs Paths of Least Resistance GND OUTPUT GND INPUT A Loop Area 1 GND OUTPUT GND INPUT B Loop Area 2 A Signal Signal µC µC A Low frequency signal return path L...

Page 529: ... slowly as possible while still maintaining sufficient throughput for all of the required system operations Harmonics of a 1 MHz system clock are less severe than harmonics of a 5 MHz system clock Differential Mode and Common Mode Radiation Differential mode and common mode noise provide the means for radiation to spread throughout a PCB onto connecting cables and out into the environment Differen...

Page 530: ...plies of radiation that can be coupled into nearby I Os These I Os can then carry the noise throughout the circuit as illustrated in the following figure Once this happens the loop area associated with the coupled noise can grow enormously In the following figure the coupling effect capacitor is not part of the design schematic but represents an actual path of high frequency noise between the OSCO...

Page 531: ...s of some common passive circuit elements Figure 6 Hidden Schematic Effects of Common Passive Circuit Elements 1 Resistor Capacitor Inductor Wire PCB trace Z F Z F Z F Z F Characteristics Ideal Real or or Low Frequency High Frequency Impedence vs Frequency The pitfalls of the high frequency schematic can be avoided with careful attention to the placement of passive circuit elements Reciprocity of ...

Page 532: ...s Floor Plan PCB First Floor planning a PCB is the first step toward designing for EMC Floor planning consists of creating zones on the PCB for analog digital and noisy components and providing proper space for grounding Also devices should be arranged to minimize routing distances of EMI critical signals such as clocks power cabling and control signals Board Zoning Board zoning allows the groundi...

Page 533: ... SPICLK of greater than 50 kHz should be placed near each other to minimize routing distances associated with these signals which tend to generate EMI Also a low impedance minimal loop area signal return ground should be provided for fast signals Moreover routing ground on both sides of a high frequency signal serves to provide some shielding for other nearby signals Grounding Along with board zon...

Page 534: ...d from each other and connected only at a low impedance ground node In a mixed signal environment the divisions between analog and digital ground may seem unclear However the analog sections of a mixed signal IC that is ADC should be provided with an analog grounding scheme and digital sections of the same IC that is CMOS digital I O including its signals and routing should be provided with a digi...

Page 535: ...ally on one side and vertically on the other side through a via It is usually more effective to lay down the ground grid before routing signals Otherwise space for a ground grid rarely is provided With this technique signals can still be routed to any area on the board and each signal is never more than one half inch from a current return path Additionally a localized VSSD digital ground plane sho...

Page 536: ...undsystemisthefoundationofadigitallogicprintedwiringboard Thereforealldigital printed wiring boards must have either a ground plane or a ground grid 3 It is important to put the ground grid on the board first before locating the signal paths 3 Critical traces need a return path less than 0 1 away 5 With regard to noise control the single most important consideration in the layout of a digital logi...

Page 537: ... µC VSSA VSSA VSSA The shortcoming of series ground connections is that more current flows through the ground closest to the beginning of the chain than through the ground toward the end of the chain Thus according to Ohm s law the series resistance of the ground trace causes the analog circuitry at one end of the series ground connections to be at a different ground potential than the analog circ...

Page 538: ... in a path with low inductance and minimized radiating loop area Routing power and ground next to each other is the next best alternative Additionally series filters such as ferrites or inductors often prove helpful for reducing noise on power supply routes A π configuration can be used on each of the VCC pins An example of a π filter appears in the figure below Figure 11 π Filter Configuration µC...

Page 539: ...ovide an engineer with the necessary tools for circuit debug for a board with buried signals Sometimes only one layer of ground plane is available If that is the case it usually should be on the outside of the board on the side with the fewest components in order to provide the best shielding effectiveness If the ground plane is buried between two signal layers its potential shielding effectivenes...

Page 540: ...holes Avoid these gaps since they deteriorate the benefits of a ground plane Signal layer connections to ground planes that is a route from the GND side of a capacitor to a via connecting it to GND should be kept as short as possible in order to take advantage of the low impedance properties of the ground plane Isolated or private line VSS3 analog ground traces can be routed on a signal layer in o...

Page 541: ...nals should have at least a small bypass ca pacitor connected to the digital ground SPI pins with greater than 50 k baud rates and the CLKOUT pin if SYSCLK is active on the pin are good candidates for bypass capacitors of 50 pF or less to VSS and series resistors The value of the series resistor depends on the loading and current drive capability of the output however 100 Ω is a good value to star...

Page 542: ...log and noisy grounds together at the lowest impedance ground node on the PCB e Connectors Provide a low impedance ground between IC s and connectors f Fast signals Run a digital ground next to fast signals or over if possible 3 Bypassing a Power Capacitors should be located as near as possible to VCC and VSS pins b Signal Capacitors should be located as near as possible to the associated pins c C...

Page 543: ...aytonR IntroductiontoElectromagneticCompatibility JohnWiley Sons Inc 1992 3 Ott Henry W Noise Reduction Techniques In Electronic Systems second edition John Wiley Sons New York 1988 4 Schneider John Automotove PCB Design Guidelines for Reduced EMI Texas Instruments 1992 5 Van Doren Tom Grounding and Shielding Electronic Systems T Van Doren 1993 ...

Page 544: ...5 Part VI Specific System Application Design Aids Part VI contains two sections EMI Reduction 503 Cost Effective Input Protection Circuitry for the Texas Instruments TMS370 Family of Microcontrollers 525 ...

Page 545: ...526 ...

Page 546: ...527 Cost Effective Input Protection Circuitry for the Texas Instruments TMS370 Family of Microcontrollers David T Maples Michael S Stewart Microcontroller Products Semiconductor Group Texas Instruments ...

Page 547: ...528 ...

Page 548: ...ging transient noise spikes The principles developed in this report are applicable to other electrically harsh environments such as industrial motor control etc Advantages of TTL Specified Input Pins Input levels of the microcontroller commonly referred to as VIL and VIH are the voltages required to guarantee that the microcontroller interprets the voltages at the device input pin as a logic one o...

Page 549: ...e of the indeterminate range and not exceeding the maximum or minimum input voltage specification of the device The following two typical conditions should be considered for the automotive environment Switching to battery voltage Vbat as illustrated by Figure 2 Switching to battery ground as illustrated by Figure 3 One of the greatest difficulties in designing external input circuitry in both cond...

Page 550: ...ing µC Input The voltage divider circuit is probably the simplest and most cost effective place to start the design of the input conditioning circuitry Figure 4 illustrates the function of a simple voltage divider circuit with the TMS370 I O buffer circuitry ...

Page 551: ...nput VCC VCC VCC µC Input IPIN Switch to VBAT Switch to ground In these figures resistor R1 holds the input voltage at a known level in an open switch condition Resistors R2 and R3 make up the resistor divider with the following familiar equation Input Voltage R3 R2 R3 VBAT Capacitor C1 and resistor R2 make up a single pole low pass filter to minimize noise detected by the software and to assist i...

Page 552: ...ÁÁ ÁÁÁÁÁÁÁÁÁ 0 6 V Once the system and microcontroller specifications have been determined an attempt can be made to find the resistor ratios necessary for the simple voltage divider circuitry that will operate over the entire Vbat range Figure 5 plots the voltages seen at the microcontroller pin versus the battery voltage fluctuations Figure 5 CMOS Input Levels Over Variations in Vbat 9 8 7 6 5 4...

Page 553: ...ÁÁÁÁÁÁÁÁÁÁÁ Parameter ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ Value ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Battery Range switch to Vbat condition ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 9 0 V VIN 18 V ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Ground Range switch to ground condition ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 2 0 V VIN 2 0 V ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Vcc ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 5 0 V 10 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Microcontroller VIH ÁÁÁÁÁ...

Page 554: ...se diode protection circuits coupled with an external current limiting resistor can be used to successfully protect the microcontroller from excessive external high voltage spikes Typically embedded microcontroller systems applications require the use of expensive external protective circuitry due tohighvoltagenoisespikespresentinthesystem Thesehighvoltagespikescaneasilyexceed the absolute maximum...

Page 555: ... protection However the TMS370 microcontroller family has been designed with internal diode protection circuitry A simple calculation can provide the necessary value for an external current limiting resistor that coupled with the internal diode protection circuitry can adequately protect the TMS370 microcontroller from external high voltage spikes Figure 8 illustrates the alternative low cost circ...

Page 556: ... external protection diodes are not needed There are two absolute maximum specifications that must be considered These are Input and output clamp current This specification is equal to 20 mA when VIN or VOUT is less than VSS2 or greater than VCCD2 Input voltage range This specification is equal to a minimum of 0 6V or a maximum of 7V on all pins except INT1 For INT1 the minimum is 0 6 V and the ma...

Page 557: ...con will not have either letter For example the device name TMS370C056 would indicate a 1 6 micron silicon design Table 4 illustrates the different types of I O pin buffer circuits used on TMS370 microcontrollers Table 4 TMS370 Microcontroller I O Pin Buffer Types ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ I O Pin Type ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ TMS370 Pins 1 2 Micron Design ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ...

Page 558: ...late the external current limiting resistor R2 value necessary to adequately protect the TMS370 microcontroller family Let s look at an example Calculation of External Current Limiting Resistor Value Example Question What minimum external resistance value R2 is needed on the AN0 pin to prevent dam age to the TMS370 device during transient voltage spikes of 150 V Conditions Limit the absolute maxim...

Page 559: ... 150 V VSSD2 0 V VPAD 0 6 V Absolute Maximum value Solve for VRINT VRINT VSSD VPAD 0 V 0 6 V 0 6 V Solve for IRINT IRINT VRINT RINT 0 6 V 20 Ω 30 mA max Since30mAexceedstheabsolutemaximumclampcurrentof20mA thefollowingequationwillsubstitute the lower value of 20 mA Solve for R2 R2 VPAD VIN IRINT 0 6 V 150 V 20 mA 149 4 V 20 mA 7 47 kΩ minimum Since the minimum external resistance R2 is larger for ...

Page 560: ...icron and 1 6 micron devices as well as a matrix to help select the minimum external resistance R2 necessary assuming an external 150 V transient condition Table 5 Typical Values of R2 Required for 1 2 and 1 6 Micron Silicon Assuming an External 150V Spike ÁÁÁÁÁÁ ÁÁÁÁÁÁ I O Pin Type ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ TMS370 Pins 1 2 Micron Design ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ TMS370 Pins 1 6 Micron Design ÁÁÁÁÁÁ ÁÁÁÁÁÁ ...

Page 561: ...o ensure that a voltage transient with some frequency content will be attenuated The values calculated for R2 and R3 should be considered minimum values Increasing the value of R2 and R3 yields the following benefits Power consumption of the microcontroller is reduced during a transient event The quiescent current of the system is reduced A greater R2 enables a lower value of C1 for an equivalent ...

Page 562: ... conditioning circuits are shown in Figure 11 This is by no means an exhaustive list but it provides a basis for cost comparison between different types of input circuits Figure 11 illustrates the simple resistor divider input conditioning circuit for Texas Instruments TMS370 family TTL inputs as well as other external protection circuits such as external diodes external zener transistor level shi...

Page 563: ...C1 Without Internal Clamp Diodes Without Internal Clamp Diodes R1 R3 R2 C1 CMOS Input With Transistor Buffer R1 R3 R2 With TTL Buffer C1 CMOS Input 1 6 74ACT11004 Vehicle Battery Vbat Vehicle Battery Vbat Vehicle Battery Vbat Vehicle Battery Vbat Vehicle Battery Vbat 5 1 V TTL Input TTL Input VCC VCC VCC ...

Page 564: ...Á ÁÁÁÁÁÁ N A ÁÁÁÁÁÁ ÁÁÁÁÁÁ N A ÁÁÁÁÁÁ ÁÁÁÁÁÁ 05 ÁÁÁÁÁ ÁÁÁÁÁ N A ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 1 6 74ACT11004 ÁÁÁÁÁ ÁÁÁÁÁ N A ÁÁÁÁÁÁ ÁÁÁÁÁÁ N A ÁÁÁÁÁÁ ÁÁÁÁÁÁ N A ÁÁÁÁÁÁ ÁÁÁÁÁÁ N A ÁÁÁÁÁ ÁÁÁÁÁ 05 ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ Totals ÁÁÁÁÁ ÁÁÁÁÁ 06 ÁÁÁÁÁÁ ÁÁÁÁÁÁ 10 ÁÁÁÁÁÁ ÁÁÁÁÁÁ 11 ÁÁÁÁÁÁ ÁÁÁÁÁÁ 15 ÁÁÁÁÁ ÁÁÁÁÁ 15 The totals shown at the bottom of Table 6 indicate that the simple resistor divider circuit used to condition Texas ...

Page 565: ...MC68HC11E9 Data Sheet Appendix A pg 2 April 1992 3 Motorola Corp 80C51 Data Sheet pg 13 3 March 1992 4 Phillips Semiconductor Corp 80C51 Data Sheet pg 142 Jan 26 1993 5 National Semiconductor Corp COP888CF Data Manual pg 7 May 1992 6 TI Advanced CMOS Logic 1988 7 TI High Speed CMOS Logic 1989 ...

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